JP6366412B2 - パターン形成方法 - Google Patents

パターン形成方法 Download PDF

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Publication number
JP6366412B2
JP6366412B2 JP2014158123A JP2014158123A JP6366412B2 JP 6366412 B2 JP6366412 B2 JP 6366412B2 JP 2014158123 A JP2014158123 A JP 2014158123A JP 2014158123 A JP2014158123 A JP 2014158123A JP 6366412 B2 JP6366412 B2 JP 6366412B2
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Japan
Prior art keywords
pattern
line
substrate
opening
openings
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Expired - Fee Related
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JP2014158123A
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English (en)
Japanese (ja)
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JP2016035967A5 (enExample
JP2016035967A (ja
Inventor
辻田　好一郎
好一郎 辻田
禎 荒井
禎 荒井
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Canon Inc
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Canon Inc
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Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2014158123A priority Critical patent/JP6366412B2/ja
Priority to US14/799,897 priority patent/US9502306B2/en
Publication of JP2016035967A publication Critical patent/JP2016035967A/ja
Publication of JP2016035967A5 publication Critical patent/JP2016035967A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • General Engineering & Computer Science (AREA)
JP2014158123A 2014-08-01 2014-08-01 パターン形成方法 Expired - Fee Related JP6366412B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014158123A JP6366412B2 (ja) 2014-08-01 2014-08-01 パターン形成方法
US14/799,897 US9502306B2 (en) 2014-08-01 2015-07-15 Pattern formation method that includes partially removing line and space pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014158123A JP6366412B2 (ja) 2014-08-01 2014-08-01 パターン形成方法

Publications (3)

Publication Number Publication Date
JP2016035967A JP2016035967A (ja) 2016-03-17
JP2016035967A5 JP2016035967A5 (enExample) 2017-09-14
JP6366412B2 true JP6366412B2 (ja) 2018-08-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014158123A Expired - Fee Related JP6366412B2 (ja) 2014-08-01 2014-08-01 パターン形成方法

Country Status (2)

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US (1) US9502306B2 (enExample)
JP (1) JP6366412B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412649B1 (en) * 2015-02-13 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device
CN107924844B (zh) * 2016-03-24 2021-07-20 东京毅力科创株式会社 半导体装置的制造方法
JP6966686B2 (ja) 2016-10-21 2021-11-17 株式会社ソシオネクスト 半導体装置
US9741823B1 (en) 2016-10-28 2017-08-22 Internation Business Machines Corporation Fin cut during replacement gate formation
KR102705024B1 (ko) 2016-12-14 2024-09-09 삼성전자주식회사 반도체 장치
US11901190B2 (en) * 2017-11-30 2024-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning
CN110828460B (zh) * 2018-08-14 2022-07-19 中芯国际集成电路制造(北京)有限公司 半导体器件及其形成方法
CN110828466B (zh) * 2019-11-11 2022-03-29 上海华力微电子有限公司 字线制作方法
JP2021153133A (ja) * 2020-03-24 2021-09-30 キオクシア株式会社 パターン形成方法およびテンプレートの製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260705A (ja) * 1999-03-12 2000-09-22 Canon Inc 露光方法ならびにそれを用いたデバイスおよびデバイス製造方法
KR100577610B1 (ko) * 2003-07-15 2006-05-10 삼성전자주식회사 반도체 장치, 반도체 장치의 제조 방법 및 에스램 장치,에스램 장치 제조 방법.
JP2005150494A (ja) * 2003-11-18 2005-06-09 Sony Corp 半導体装置の製造方法
US7759242B2 (en) * 2007-08-22 2010-07-20 Qimonda Ag Method of fabricating an integrated circuit
KR100934836B1 (ko) * 2008-06-19 2009-12-31 주식회사 하이닉스반도체 반도체소자의 미세패턴 형성방법
KR101618749B1 (ko) * 2009-02-27 2016-05-09 삼성전자주식회사 반도체 소자의 패턴 형성 방법
JP4901898B2 (ja) * 2009-03-30 2012-03-21 株式会社東芝 半導体装置の製造方法
JP5499641B2 (ja) * 2009-11-04 2014-05-21 富士通セミコンダクター株式会社 半導体装置及びその設計方法並びに半導体装置の製造方法
JP2011258822A (ja) * 2010-06-10 2011-12-22 Toshiba Corp 半導体装置の製造方法
JP2012033923A (ja) * 2010-07-29 2012-02-16 Nikon Corp 露光方法及び露光装置、並びにデバイス製造方法
US8795953B2 (en) * 2010-09-14 2014-08-05 Nikon Corporation Pattern forming method and method for producing device
CN102683191B (zh) * 2011-03-17 2014-08-27 中芯国际集成电路制造(上海)有限公司 形成栅极图案的方法以及半导体装置
JP5798502B2 (ja) * 2012-01-31 2015-10-21 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US9236267B2 (en) * 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
JP5881567B2 (ja) * 2012-08-29 2016-03-09 株式会社東芝 パターン形成方法
JP6347329B2 (ja) * 2012-10-19 2018-06-27 株式会社ニコン パターン形成方法及びデバイス製造方法
US9349604B2 (en) * 2013-10-20 2016-05-24 Tokyo Electron Limited Use of topography to direct assembly of block copolymers in grapho-epitaxial applications
US9224617B2 (en) * 2014-01-29 2015-12-29 Globalfoundries Inc. Forming cross-coupled line segments
US9287131B2 (en) * 2014-02-21 2016-03-15 Globalfoundries Inc. Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules

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Publication number Publication date
US9502306B2 (en) 2016-11-22
US20160035628A1 (en) 2016-02-04
JP2016035967A (ja) 2016-03-17

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