JP6351371B2 - 弾性波デバイス - Google Patents
弾性波デバイス Download PDFInfo
- Publication number
- JP6351371B2 JP6351371B2 JP2014103709A JP2014103709A JP6351371B2 JP 6351371 B2 JP6351371 B2 JP 6351371B2 JP 2014103709 A JP2014103709 A JP 2014103709A JP 2014103709 A JP2014103709 A JP 2014103709A JP 6351371 B2 JP6351371 B2 JP 6351371B2
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- JP
- Japan
- Prior art keywords
- chip
- acoustic wave
- active element
- chips
- ceiling portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Description
12 デバイスチップ
12a SAWフィルタチップ
12b 能動素子チップ
24 金属パターン
26 側壁部
28 天井部
28a 金属リッド
28b 半田
30 金属封止部
34、34a 圧力領域
100〜300 弾性波デバイス
Claims (5)
- 実装基板上にフリップチップ実装され、弾性波チップと能動素子チップとを含む複数のデバイスチップと、
前記実装基板上に設けられ、前記複数のデバイスチップの周りを囲む金属製の側壁部と前記複数のデバイスチップ上から前記側壁部上に延在する金属製の天井部とを含み、前記複数のデバイスチップを封止する金属封止部と、を備え、
前記複数のデバイスチップのうちの前記弾性波チップの上面は前記天井部に接触し、前記複数のデバイスチップのうちの前記能動素子チップの上面は前記天井部との間に空隙が形成されて前記天井部に接触してなく、
前記側壁部の前記天井部に接触する部分の面積は、前記弾性波チップの上面の前記天井部に接触する部分の面積よりも大きいことを特徴とする弾性波デバイス。 - 前記能動素子チップはパワーアンプ又はローノイズアンプを含むことを特徴とする請求項1記載の弾性波デバイス。
- 前記複数のデバイスチップのうち前記実装基板の中央部分に実装されたデバイスチップの上面は前記天井部に接触することを特徴とする請求項1または2記載の弾性波デバイス。
- 前記天井部は、平坦形状をした金属リッドを含み、
前記側壁部は、半田からなることを特徴とする請求項1から3のいずれか一項記載の弾性波デバイス。 - 前記金属封止部は、前記複数のデバイスチップの間には設けられていないことを特徴とする請求項1から4のいずれか一項記載の弾性波デバイス。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014103709A JP6351371B2 (ja) | 2014-05-19 | 2014-05-19 | 弾性波デバイス |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014103709A JP6351371B2 (ja) | 2014-05-19 | 2014-05-19 | 弾性波デバイス |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015220645A JP2015220645A (ja) | 2015-12-07 |
JP6351371B2 true JP6351371B2 (ja) | 2018-07-04 |
Family
ID=54779696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014103709A Active JP6351371B2 (ja) | 2014-05-19 | 2014-05-19 | 弾性波デバイス |
Country Status (1)
Country | Link |
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JP (1) | JP6351371B2 (ja) |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09293808A (ja) * | 1996-04-25 | 1997-11-11 | Fujitsu Ltd | 半導体装置 |
CN101401206B (zh) * | 2006-03-29 | 2011-04-13 | 京瓷株式会社 | 电路组件和无线通信设备、以及电路组件的制造方法 |
JP5561460B2 (ja) * | 2009-06-03 | 2014-07-30 | 新光電気工業株式会社 | 配線基板および配線基板の製造方法 |
US8976529B2 (en) * | 2011-01-14 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lid design for reliability enhancement in flip chip package |
JP2012182395A (ja) * | 2011-03-02 | 2012-09-20 | Taiyo Yuden Co Ltd | 電子デバイス |
JP2013131711A (ja) * | 2011-12-22 | 2013-07-04 | Taiyo Yuden Co Ltd | 電子部品 |
JP6060527B2 (ja) * | 2012-05-31 | 2017-01-18 | 株式会社ソシオネクスト | 半導体パッケージ |
-
2014
- 2014-05-19 JP JP2014103709A patent/JP6351371B2/ja active Active
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Publication number | Publication date |
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JP2015220645A (ja) | 2015-12-07 |
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