JP6342156B2 - 受動素子内蔵基板 - Google Patents
受動素子内蔵基板 Download PDFInfo
- Publication number
- JP6342156B2 JP6342156B2 JP2013266555A JP2013266555A JP6342156B2 JP 6342156 B2 JP6342156 B2 JP 6342156B2 JP 2013266555 A JP2013266555 A JP 2013266555A JP 2013266555 A JP2013266555 A JP 2013266555A JP 6342156 B2 JP6342156 B2 JP 6342156B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- pattern layer
- passive element
- substrate
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09854—Hole or via having special cross-section, e.g. elliptical
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
11 第1ビアの上部面
12 第1ビアの下部面
20 第2ビア
21 第2ビアの下部面
22 第2ビアの上部面
30 第3ビア
40 第4ビア
50 第5ビア
100 能動素子
110 外部端子
210 第1絶縁層
211 キャビティ
221 第2絶縁層
222 第3絶縁層
300 受動素子
310 外部電極
P1 第1導体パターン層
P2 第2導体パターン層
P21 第3導体パターン層
P22 第4導体パターン層
1000、2000 受動素子内蔵基板
Claims (6)
- 外部電極を有する受動素子が内蔵された絶縁層と、
前記絶縁層の下部面に備えられる第1導体パターン層と、
前記絶縁層の上部面に備えられる第2導体パターン層と、
前記第2導体パターン層の上側に実装される能動素子と、
前記外部電極の下部面と前記第1導体パターン層との間を電気的に連結する第1ビアと、
前記外部電極の上部面と前記第2導体パターン層との間を電気的に連結し、前記第1ビアより体積が小さい第2ビアと、を含み、
前記能動素子と前記受動素子が、前記第2ビアを経由する第1経路と、前記第1ビアを経由する第2経路と、によって、電気的に連結された受動素子内蔵基板。 - 前記絶縁層が、第1絶縁層と、当該第1絶縁層の上に備えられる第2絶縁層及び第1絶縁層の下に備えられる第3絶縁層を有し、
前記第1絶縁層の下部面に備えられる第3導体パターン層と、
前記第1絶縁層の上部面に備えられる第4導体パターン層と、
前記第1絶縁層を貫通し、前記第3導体パターン層と第4導体パターン層との間を電気的に連結する第4ビアと、
前記第1導体パターン層と前記第3導体パターン層との間を電気的に連結する第3ビアと、
前記第2導体パターン層と前記第4導体パターン層との間を電気的に連結する第5ビアと、
を備え、
前記第1経路が、前記第2ビアと前記第2導体パターン層を経由する経路であり、
前記第2経路が、前記第1ビア、前記第1導体パターン層、前記第3ビア、前記第3導体パターン層、前記第4ビア、前記第4導体パターン層、前記第5ビア、前記第2導体パターン層を経由する経路であることを特徴とする、請求項1に記載の受動素子内蔵基板。 - 前記第1ビア1個と前記外部電極の下部面とが接する面の断面積は、前記第2ビア1個と前記外部電極の上部面とが接する面の断面積より大きいことを特徴とする、請求項2に記載の受動素子内蔵基板。
- 前記第1ビア1個と前記第1導体パターン層とが接する面の断面積は、前記第2ビア1個と前記第2導体パターン層とが接する面の断面積より大きいことを特徴とする、請求項2に記載の受動素子内蔵基板。
- 前記第1ビアの個数は第2ビアの個数より多いことを特徴とする、請求項2に記載の受動素子内蔵基板。
- 前記受動素子は、積層セラミックキャパシタであることを特徴とする、請求項1に記載の受動素子内蔵基板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020120158335A KR101472638B1 (ko) | 2012-12-31 | 2012-12-31 | 수동소자 내장기판 |
KR10-2012-0158335 | 2012-12-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014131039A JP2014131039A (ja) | 2014-07-10 |
JP6342156B2 true JP6342156B2 (ja) | 2018-06-13 |
Family
ID=51016985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013266555A Expired - Fee Related JP6342156B2 (ja) | 2012-12-31 | 2013-12-25 | 受動素子内蔵基板 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9420683B2 (ja) |
JP (1) | JP6342156B2 (ja) |
KR (1) | KR101472638B1 (ja) |
TW (1) | TWI556362B (ja) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102295105B1 (ko) * | 2014-12-29 | 2021-08-31 | 삼성전기주식회사 | 회로기판 및 회로기판 제조방법 |
DE102015104641A1 (de) * | 2015-03-26 | 2016-09-29 | At & S Austria Technologie & Systemtechnik Ag | Träger mit passiver Kühlfunktion für ein Halbleiterbauelement |
WO2016170894A1 (ja) * | 2015-04-21 | 2016-10-27 | 株式会社村田製作所 | 配線基板及び積層チップコンデンサ |
KR20170034712A (ko) | 2015-09-21 | 2017-03-29 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판의 제조방법 |
TWI672768B (zh) * | 2016-01-15 | 2019-09-21 | 英屬開曼群島商鳳凰先驅股份有限公司 | 封裝基板 |
US9743526B1 (en) * | 2016-02-10 | 2017-08-22 | International Business Machines Corporation | Wiring board with stacked embedded capacitors and method of making |
JP2017204511A (ja) * | 2016-05-10 | 2017-11-16 | ソニー株式会社 | 半導体装置、半導体装置の製造方法、及び、電子機器 |
KR101952863B1 (ko) * | 2016-06-21 | 2019-02-28 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
US9935068B2 (en) | 2016-06-21 | 2018-04-03 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
KR20190092584A (ko) * | 2016-12-29 | 2019-08-07 | 인벤사스 본딩 테크놀로지스 인코포레이티드 | 집적된 수동 컴포넌트를 구비한 접합된 구조체 |
JP6897139B2 (ja) * | 2017-02-13 | 2021-06-30 | Tdk株式会社 | 電子部品内蔵基板及び基板実装構造体 |
JP6822192B2 (ja) * | 2017-02-13 | 2021-01-27 | Tdk株式会社 | 電子部品内蔵基板 |
KR102099749B1 (ko) | 2018-01-19 | 2020-04-10 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
US11380616B2 (en) * | 2018-05-16 | 2022-07-05 | Intel IP Corporation | Fan out package-on-package with adhesive die attach |
KR102632363B1 (ko) * | 2018-12-07 | 2024-02-02 | 삼성전기주식회사 | 브리지 내장기판 및 반도체 패키지 |
KR102595865B1 (ko) * | 2019-03-04 | 2023-10-30 | 삼성전자주식회사 | 하이브리드 인터포저를 갖는 반도체 패키지 |
US11901281B2 (en) | 2019-03-11 | 2024-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with integrated passive component |
JP7455516B2 (ja) | 2019-03-29 | 2024-03-26 | Tdk株式会社 | 素子内蔵基板およびその製造方法 |
KR102231104B1 (ko) * | 2019-12-27 | 2021-03-23 | 삼성전기주식회사 | 저항 부품 |
US11502710B2 (en) | 2020-02-05 | 2022-11-15 | Samsung Electro-Mechanics Co., Ltd. | Front-end module |
KR20220001634A (ko) * | 2020-06-30 | 2022-01-06 | 삼성전기주식회사 | 인쇄회로기판 |
TW202315470A (zh) * | 2021-06-10 | 2023-04-01 | 韓商Lg伊諾特股份有限公司 | 電路板及具有該電路板之半導體封裝 |
KR20230075176A (ko) * | 2021-11-22 | 2023-05-31 | 삼성전기주식회사 | 인쇄회로기판 |
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JP4851652B2 (ja) | 2000-02-09 | 2012-01-11 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
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US8745860B2 (en) * | 2011-03-11 | 2014-06-10 | Ibiden Co., Ltd. | Method for manufacturing printed wiring board |
US8891245B2 (en) * | 2011-09-30 | 2014-11-18 | Ibiden Co., Ltd. | Printed wiring board |
-
2012
- 2012-12-31 KR KR1020120158335A patent/KR101472638B1/ko active IP Right Grant
-
2013
- 2013-12-06 TW TW102144750A patent/TWI556362B/zh not_active IP Right Cessation
- 2013-12-25 JP JP2013266555A patent/JP6342156B2/ja not_active Expired - Fee Related
- 2013-12-30 US US14/143,727 patent/US9420683B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR20140087740A (ko) | 2014-07-09 |
US20140185258A1 (en) | 2014-07-03 |
JP2014131039A (ja) | 2014-07-10 |
KR101472638B1 (ko) | 2014-12-15 |
TWI556362B (zh) | 2016-11-01 |
TW201431012A (zh) | 2014-08-01 |
US9420683B2 (en) | 2016-08-16 |
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