JP6318084B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

Info

Publication number
JP6318084B2
JP6318084B2 JP2014254997A JP2014254997A JP6318084B2 JP 6318084 B2 JP6318084 B2 JP 6318084B2 JP 2014254997 A JP2014254997 A JP 2014254997A JP 2014254997 A JP2014254997 A JP 2014254997A JP 6318084 B2 JP6318084 B2 JP 6318084B2
Authority
JP
Japan
Prior art keywords
wiring layer
electronic component
plated wiring
resin
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014254997A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016115870A5 (https=
JP2016115870A (ja
Inventor
亮 深澤
亮 深澤
堀内　道夫
道夫 堀内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2014254997A priority Critical patent/JP6318084B2/ja
Priority to US14/946,953 priority patent/US9721876B2/en
Publication of JP2016115870A publication Critical patent/JP2016115870A/ja
Publication of JP2016115870A5 publication Critical patent/JP2016115870A5/ja
Application granted granted Critical
Publication of JP6318084B2 publication Critical patent/JP6318084B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/417—Bonding materials between chips and die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2014254997A 2014-12-17 2014-12-17 半導体装置及びその製造方法 Active JP6318084B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014254997A JP6318084B2 (ja) 2014-12-17 2014-12-17 半導体装置及びその製造方法
US14/946,953 US9721876B2 (en) 2014-12-17 2015-11-20 Semiconductor device and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014254997A JP6318084B2 (ja) 2014-12-17 2014-12-17 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2016115870A JP2016115870A (ja) 2016-06-23
JP2016115870A5 JP2016115870A5 (https=) 2017-08-17
JP6318084B2 true JP6318084B2 (ja) 2018-04-25

Family

ID=56130319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014254997A Active JP6318084B2 (ja) 2014-12-17 2014-12-17 半導体装置及びその製造方法

Country Status (2)

Country Link
US (1) US9721876B2 (https=)
JP (1) JP6318084B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10229901B2 (en) * 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
JP2018107394A (ja) 2016-12-28 2018-07-05 新光電気工業株式会社 配線基板及び電子部品装置とそれらの製造方法
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001015644A (ja) * 1999-06-28 2001-01-19 Toshiba Corp 半導体パッケージ及びその製造方法
AU2003299866A1 (en) * 2003-02-25 2004-09-28 Tessera, Inc. High frequency chip packages with connecting elements
JP2004319530A (ja) * 2003-02-28 2004-11-11 Sanyo Electric Co Ltd 光半導体装置およびその製造方法
JP4243178B2 (ja) * 2003-12-25 2009-03-25 新光電気工業株式会社 半導体装置の製造方法
US20060091516A1 (en) * 2004-11-01 2006-05-04 Akira Matsunami Flexible leaded stacked semiconductor package
US7462925B2 (en) * 2004-11-12 2008-12-09 Macronix International Co., Ltd. Method and apparatus for stacking electrical components using via to provide interconnection
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
US8093694B2 (en) * 2005-02-14 2012-01-10 Stats Chippac Ltd. Method of manufacturing non-leaded integrated circuit package system having etched differential height lead structures
JP4897451B2 (ja) 2006-12-04 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置
JP2009026960A (ja) * 2007-07-19 2009-02-05 Mitsubishi Electric Corp 半導体装置
JP5068133B2 (ja) * 2007-10-17 2012-11-07 新光電気工業株式会社 半導体チップ積層構造体及び半導体装置
JP5707902B2 (ja) * 2010-12-02 2015-04-30 ソニー株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
US9721876B2 (en) 2017-08-01
US20160181190A1 (en) 2016-06-23
JP2016115870A (ja) 2016-06-23

Similar Documents

Publication Publication Date Title
EP2852974B1 (en) Method of making a substrate-less stackable package with wire-bond interconnect
CN106711104B (zh) 封装基板及其制作工艺、半导体元件封装结构及制作工艺
KR101772284B1 (ko) 반도체 디바이스 및 그 제조 방법
JP2017022408A (ja) ２重エッチングフリップチップコネクタ又は多重エッチングフリップチップコネクタを有する超小型電子パッケージ及び対応する製造方法
JP2017038075A (ja) エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ
CN108461406B (zh) 衬底结构、半导体封装结构及其制造方法
CN101276809A (zh) 半导体器件及其制造方法
CN101911291A (zh) 具有用于镀敷芯片下方的垫的迹线的球栅阵列封装
JP5151158B2 (ja) パッケージ、およびそのパッケージを用いた半導体装置
JP7012489B2 (ja) 半導体装置
JP4489575B2 (ja) 半導体装置及びその製造方法
JP2006310530A (ja) 回路装置およびその製造方法
JP6318084B2 (ja) 半導体装置及びその製造方法
JP5404513B2 (ja) 半導体装置の製造方法
TWI452659B (zh) 電路板及其製作方法與封裝結構
CN105720038A (zh) 具有挠性互连结构的芯片尺寸封装
JP2016136613A (ja) 半導体装置の製造方法および半導体装置
JP4887170B2 (ja) 半導体装置の製造方法
JP2009164493A (ja) 配線基板及びその製造方法並びに電子部品装置及びその製造方法
JP4631223B2 (ja) 半導体実装体およびそれを用いた半導体装置
JP2012023409A (ja) 回路装置およびその製造方法
CN110265384A (zh) 封装结构
JP7154818B2 (ja) 半導体装置および半導体装置の製造方法
JP2018088505A (ja) 半導体装置およびその製造方法
JP4887948B2 (ja) 半導体装置及び半導体モジュール

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170703

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170703

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180226

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180320

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180402

R150 Certificate of patent or registration of utility model

Ref document number: 6318084

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150