JP6318084B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP6318084B2
JP6318084B2 JP2014254997A JP2014254997A JP6318084B2 JP 6318084 B2 JP6318084 B2 JP 6318084B2 JP 2014254997 A JP2014254997 A JP 2014254997A JP 2014254997 A JP2014254997 A JP 2014254997A JP 6318084 B2 JP6318084 B2 JP 6318084B2
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Japan
Prior art keywords
wiring layer
electronic component
plated wiring
resin
cavity
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JP2014254997A
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English (en)
Japanese (ja)
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JP2016115870A (ja
JP2016115870A5 (enExample
Inventor
亮 深澤
亮 深澤
堀内　道夫
道夫 堀内
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2014254997A priority Critical patent/JP6318084B2/ja
Priority to US14/946,953 priority patent/US9721876B2/en
Publication of JP2016115870A publication Critical patent/JP2016115870A/ja
Publication of JP2016115870A5 publication Critical patent/JP2016115870A5/ja
Application granted granted Critical
Publication of JP6318084B2 publication Critical patent/JP6318084B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Geometry (AREA)
JP2014254997A 2014-12-17 2014-12-17 半導体装置及びその製造方法 Active JP6318084B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014254997A JP6318084B2 (ja) 2014-12-17 2014-12-17 半導体装置及びその製造方法
US14/946,953 US9721876B2 (en) 2014-12-17 2015-11-20 Semiconductor device and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014254997A JP6318084B2 (ja) 2014-12-17 2014-12-17 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2016115870A JP2016115870A (ja) 2016-06-23
JP2016115870A5 JP2016115870A5 (enExample) 2017-08-17
JP6318084B2 true JP6318084B2 (ja) 2018-04-25

Family

ID=56130319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014254997A Active JP6318084B2 (ja) 2014-12-17 2014-12-17 半導体装置及びその製造方法

Country Status (2)

Country Link
US (1) US9721876B2 (enExample)
JP (1) JP6318084B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10229901B2 (en) * 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
JP2018107394A (ja) * 2016-12-28 2018-07-05 新光電気工業株式会社 配線基板及び電子部品装置とそれらの製造方法
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001015644A (ja) * 1999-06-28 2001-01-19 Toshiba Corp 半導体パッケージ及びその製造方法
JP4504204B2 (ja) * 2003-02-25 2010-07-14 テッセラ，インコーポレイテッド 接続要素を有する高周波チップパッケージ
JP2004319530A (ja) * 2003-02-28 2004-11-11 Sanyo Electric Co Ltd 光半導体装置およびその製造方法
JP4243178B2 (ja) * 2003-12-25 2009-03-25 新光電気工業株式会社 半導体装置の製造方法
US20060091516A1 (en) * 2004-11-01 2006-05-04 Akira Matsunami Flexible leaded stacked semiconductor package
US7462925B2 (en) * 2004-11-12 2008-12-09 Macronix International Co., Ltd. Method and apparatus for stacking electrical components using via to provide interconnection
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
US8093694B2 (en) * 2005-02-14 2012-01-10 Stats Chippac Ltd. Method of manufacturing non-leaded integrated circuit package system having etched differential height lead structures
JP4897451B2 (ja) 2006-12-04 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置
JP2009026960A (ja) * 2007-07-19 2009-02-05 Mitsubishi Electric Corp 半導体装置
JP5068133B2 (ja) * 2007-10-17 2012-11-07 新光電気工業株式会社 半導体チップ積層構造体及び半導体装置
JP5707902B2 (ja) * 2010-12-02 2015-04-30 ソニー株式会社 半導体装置及びその製造方法

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Publication number Publication date
JP2016115870A (ja) 2016-06-23
US9721876B2 (en) 2017-08-01
US20160181190A1 (en) 2016-06-23

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