JP2016115870A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2016115870A5 JP2016115870A5 JP2014254997A JP2014254997A JP2016115870A5 JP 2016115870 A5 JP2016115870 A5 JP 2016115870A5 JP 2014254997 A JP2014254997 A JP 2014254997A JP 2014254997 A JP2014254997 A JP 2014254997A JP 2016115870 A5 JP2016115870 A5 JP 2016115870A5
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- wiring layer
- plated wiring
- forming
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010410 layer Substances 0.000 claims description 43
- 239000011347 resin Substances 0.000 claims description 26
- 229920005989 resin Polymers 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000002356 single layer Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 4
- 238000004519 manufacturing process Methods 0.000 claims 3
- 238000000034 method Methods 0.000 claims 2
- 239000000463 material Substances 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014254997A JP6318084B2 (ja) | 2014-12-17 | 2014-12-17 | 半導体装置及びその製造方法 |
| US14/946,953 US9721876B2 (en) | 2014-12-17 | 2015-11-20 | Semiconductor device and method of making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014254997A JP6318084B2 (ja) | 2014-12-17 | 2014-12-17 | 半導体装置及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016115870A JP2016115870A (ja) | 2016-06-23 |
| JP2016115870A5 true JP2016115870A5 (enExample) | 2017-08-17 |
| JP6318084B2 JP6318084B2 (ja) | 2018-04-25 |
Family
ID=56130319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014254997A Active JP6318084B2 (ja) | 2014-12-17 | 2014-12-17 | 半導体装置及びその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9721876B2 (enExample) |
| JP (1) | JP6318084B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10229901B2 (en) * | 2016-06-27 | 2019-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Immersion interconnections for semiconductor devices and methods of manufacture thereof |
| JP2018107394A (ja) * | 2016-12-28 | 2018-07-05 | 新光電気工業株式会社 | 配線基板及び電子部品装置とそれらの製造方法 |
| US10957672B2 (en) * | 2017-11-13 | 2021-03-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001015644A (ja) * | 1999-06-28 | 2001-01-19 | Toshiba Corp | 半導体パッケージ及びその製造方法 |
| JP4504204B2 (ja) * | 2003-02-25 | 2010-07-14 | テッセラ,インコーポレイテッド | 接続要素を有する高周波チップパッケージ |
| JP2004319530A (ja) * | 2003-02-28 | 2004-11-11 | Sanyo Electric Co Ltd | 光半導体装置およびその製造方法 |
| JP4243178B2 (ja) * | 2003-12-25 | 2009-03-25 | 新光電気工業株式会社 | 半導体装置の製造方法 |
| US20060091516A1 (en) * | 2004-11-01 | 2006-05-04 | Akira Matsunami | Flexible leaded stacked semiconductor package |
| US7462925B2 (en) * | 2004-11-12 | 2008-12-09 | Macronix International Co., Ltd. | Method and apparatus for stacking electrical components using via to provide interconnection |
| JP2006165175A (ja) * | 2004-12-06 | 2006-06-22 | Alps Electric Co Ltd | 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法 |
| US8093694B2 (en) * | 2005-02-14 | 2012-01-10 | Stats Chippac Ltd. | Method of manufacturing non-leaded integrated circuit package system having etched differential height lead structures |
| JP4897451B2 (ja) | 2006-12-04 | 2012-03-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2009026960A (ja) * | 2007-07-19 | 2009-02-05 | Mitsubishi Electric Corp | 半導体装置 |
| JP5068133B2 (ja) * | 2007-10-17 | 2012-11-07 | 新光電気工業株式会社 | 半導体チップ積層構造体及び半導体装置 |
| JP5707902B2 (ja) * | 2010-12-02 | 2015-04-30 | ソニー株式会社 | 半導体装置及びその製造方法 |
-
2014
- 2014-12-17 JP JP2014254997A patent/JP6318084B2/ja active Active
-
2015
- 2015-11-20 US US14/946,953 patent/US9721876B2/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2016072493A5 (enExample) | ||
| KR101640309B1 (ko) | 관통 몰딩 비아를 갖는 패키지 온 패키지 구조체를 포함하는 반도체 디바이스 및 그 형성 방법 | |
| CN104241219A (zh) | 元件嵌入式封装结构和其制造方法 | |
| JP2016096292A5 (enExample) | ||
| JP2011258772A5 (enExample) | ||
| US20150325559A1 (en) | Embedded package and method thereof | |
| JP2013538467A5 (enExample) | ||
| JP2013229542A5 (enExample) | ||
| JP2013118255A5 (enExample) | ||
| JP2013026625A5 (enExample) | ||
| JP2015070007A5 (enExample) | ||
| JP2010267805A5 (enExample) | ||
| EP2988325A3 (en) | Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof | |
| JP2015015313A5 (enExample) | ||
| JP2017135290A5 (enExample) | ||
| JP2015159197A5 (enExample) | ||
| JP2016092300A5 (enExample) | ||
| JP2016072492A5 (enExample) | ||
| JP2018125349A5 (enExample) | ||
| JP2018107267A5 (enExample) | ||
| JP2017011075A5 (enExample) | ||
| JP2016092259A5 (enExample) | ||
| JP2017050310A5 (enExample) | ||
| TW201618247A (zh) | 封裝結構及其製法 | |
| JP2014160798A5 (enExample) |