CN104241219A - 元件嵌入式封装结构和其制造方法 - Google Patents

元件嵌入式封装结构和其制造方法 Download PDF

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Publication number
CN104241219A
CN104241219A CN201410424606.8A CN201410424606A CN104241219A CN 104241219 A CN104241219 A CN 104241219A CN 201410424606 A CN201410424606 A CN 201410424606A CN 104241219 A CN104241219 A CN 104241219A
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China
Prior art keywords
patterned conductive
conductive layer
substrate
hole
nude film
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Granted
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CN201410424606.8A
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CN104241219B (zh
Inventor
李志成
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN201410424606.8A priority Critical patent/CN104241219B/zh
Publication of CN104241219A publication Critical patent/CN104241219A/zh
Priority to US14/732,529 priority patent/US9721899B2/en
Priority to CN201610395511.7A priority patent/CN106252300B/zh
Priority to CN201811579751.8A priority patent/CN110071076B/zh
Priority to US15/635,128 priority patent/US10276507B2/en
Application granted granted Critical
Publication of CN104241219B publication Critical patent/CN104241219B/zh
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Abstract

本发明涉及一种元件嵌入式封装结构和其制造方法。所述元件嵌入式封装结构包含：衬底，具有第一表面和相对于所述第一表面的第二表面，和从所述第一表面延伸到所述第二表面的通孔；第一电性互连件，从所述第一表面延伸到所述第二表面；第一图案化导电层设置于所述第一表面上；第二图案化导电层设置于所述第二表面上，透过所述第一电性互连件与所述第一图案化导电层电性连接；至少一个裸片设置于所述通孔中，所述裸片具有主动面和相对于所述主动面的背面，所述裸片的背面是露出于所述衬底的第二表面；第一介电层，填入所述裸片与所述通孔的侧壁之间的空隙并且覆盖所述裸片的所述主动面和所述衬底的第一表面；第三图案化导电层设置于所述第一介电层的表面上，透过第二电性互连件与所述裸片电性连接；以及金属层，直接设置于所述裸片的背面上。

Description

元件嵌入式封装结构和其制造方法
技术领域
本发明涉及一种半导体封装和其制造方法。
背景技术
因应电子产品小尺寸和效能的需求，电子产品的关键组件，即半导体元件的设计越趋复杂并且被要求要更加的微型化。一般说来，半导体元件会安装于含有电路的衬底上，再封装。但，如此一来，衬底上的空间便有部份为所述半导体封装件所占据，减少进一步往上堆叠晶片的可能性。因此，目前技术研发的方向便朝向将元件埋置于衬底中，以减少半导体元件在衬底上所占据的空间并简化组装过程的技术。但，因半导体元件是埋置于衬底内，其散热效果便成为棘手的问题。
发明内容
本发明的一方面涉及一种元件嵌入式封装结构。在一个实施例中，所述元件嵌入式封装结构包含：衬底，具有第一表面和相对于所述第一表面的第二表面，和从所述第一表面延伸到所述第二表面的通孔；第一电性互连件，从所述第一表面延伸到所述第二表面；第一图案化导电层设置于所述第一表面上；第二图案化导电层设置于所述第二表面上，透过所述第一电性互连件与所述第一图案化导电层电性连接；至少一裸片设置于所述通孔中，所述裸片具有主动面和相对于所述主动面的背面，所述裸片的背面是露出于所述衬底的第二表面；第一介电层，填入所述裸片与所述通孔的侧壁之间的空隙并且覆盖所述裸片的所述主动面和所述衬底的第一表面；第三图案化导电层设置于所述第一介电层的表面上，透过第二电性互连件与所述裸片电性连接；和金属层，直接设置于所述裸片的背面上。
本发明的另一方面涉及一种制造元件嵌入式封装结构的方法。在一个实施例中，所述方法包含：提供衬底，所述衬底具有上表面和下表面；形成从所述衬底的上表面延伸到所述衬底的下表面的第一通孔；形成电性互连件于所述第一通孔中；形成第一图案化导电层于所述衬底的下表面上和形成第二图案化导电层于所述衬底的上表面上，其中所述第一图案化导电层与所述第二图案化导电层是透过所述电性互连件电性连接；在所述第一通孔的侧边形成从所述衬底的上表面延伸到所述衬底的下表面的第二通孔；配置粘性膜在所述衬底的下表面上，涵盖全部或部份的所述第二通孔范围；配置至少一个裸片于所述第二通孔中，附着于所述粘性膜上；提供介电层覆盖于所述裸片的所述上表面；移除所述粘性膜，露出所述至少一个裸片的背面；和电镀一个金属层于所述至少一裸片的背面。
在另一实施例中，所述方法包含：提供衬底，所述衬底具有上表面和下表面；形成第一图案化导电层于所述衬底的上表面上；形成从所述衬底的上表面延伸到所述衬底的下表面的第一通孔；配置粘性膜在所述衬底的下表面上，涵盖全部或部份的所述第一通孔范围；配置至少一个裸片于所述第一通孔中，附着于所述粘性膜上；提供介电层覆盖于所述至少一个裸片的所述上表面；移除所述粘性膜，露出所述至少一个裸片的背面；形成从所述衬底的下表面延伸到所述衬底的上表面的第二通孔；形成电性互连件于所述第二通孔中；形成第二图案化导电层于所述衬底的下表面上，其中所述第一图案化导电层与所述第二图案化导电层是透过所述电性互连件电性连接；和电镀金属层于所述至少一个裸片的背面。
本发明的其它方面和实施例亦涵盖。前述的发明内容和以下的说明并非旨在将本发明限制于任何特定的实施例，而是仅用于说明本发明的某些实施例。
附图说明
图1显示根据本发明元件嵌入式封装结构的实施例的剖面图。
图2显示根据本发明元件嵌入式封装结构的另一实施例的剖面图。
图3显示根据本发明元件嵌入式封装结构的另一实施例的剖面图。
图4显示根据本发明元件嵌入式封装结构的另一实施例的剖面图。
图5显示根据本发明元件嵌入式封装结构的另一实施例的剖面图。
图6显示根据本发明元件嵌入式封装结构的另一实施例的剖面图。
图7显示根据本发明元件嵌入式封装结构的另一实施例的剖面图。
图8显示根据本发明元件嵌入式封装结构的另一实施例的剖面图。
图9A到9M绘示根据本发明的元件嵌入式封装结构的方法的多个实施例。
图10A到10I绘示根据本发明的元件嵌入式封装结构的方法的多个实施例。
绘示本发明实施例的图式和其相关说明，是用于解释本发明的某些实施例的原则。
具体实施方式
请参考图1，其绘示根据本发明元件嵌入式封装结构的实施例的剖面图。所述元件嵌入式封装结构100包括裸片102、衬底104、金属层106、第一介电层108、第一图案化导电层110、第二图案化导电层112、第三图案化导电层114和防焊层116。
所述裸片102具有主动面102a、相对于所述主动面102a的背面102b和侧面102c。所述裸片102的背面102b是直接与所述金属层106接触。
所述衬底104具有第一表面104a和相对于所述第一表面104a的第二表面104b。在实施例中，所述衬底104具有从所述第一表面104a延伸到所述第二表面104b的至少一个用于容纳至少一个裸片的第一通孔104c。所述第一通孔104c的宽度和形状是根据所述裸片的尺寸、数量和形状所设计。所述第一通孔104c的宽度应大于等于所述裸片的尺寸，以容纳所述裸片。所述第一通孔104c的侧壁与所述裸片102的侧面102c间可具有空隙。所述第一通孔104c的深度可以大于、等于或小于所述裸片102的高度。在实施例中，所述裸片102的高度是大于所述第一通孔104c的深度，由此，可降低电性互连件120的高度，使得后续利用镀膜形成电性互连件的制程较容易控制。在另一实施例中，所述裸片102的高度不大于(小于等于)所述第一通孔104c的深度，由此，可降低第一介电层108的厚度，进而降低封装的厚度。所述第一通孔104c的侧壁可具有斜度，使靠近所述第一通孔104c底部的侧壁较靠近所述第一通孔104c顶部的侧壁较远离所述裸片，由此，可增加电镀金属层106的面积，进而增加电镀金属层106的一致性。在实施例中，所述侧壁可具有弧度。
如图1所示，所述衬底104可形成至少一个第二通孔在所述第一通孔104c的侧边，从所述衬底104的第一表面104a延伸到所述衬底104的第二表面104b。所述第二通孔中可设有第一电性互连件122。所述第二通孔可具有任何形状，包含但不限于：柱状(如圆柱状、椭圆柱状、方形柱状或矩形柱状)，或非柱状(如圆锥状、漏斗状或其它锥状)。所述通孔的侧壁可具有弧度或具有纹理。在实施例中，所述第一电性互连件122曝露在所述第一表面104a的面积小于所述第一电性互连件122曝露在所述第二表面104b的面积。
在实施例中，所述衬底104是芯材衬底。所述芯材衬底可包含聚合性或非聚合性材料。例如，所述芯材衬底可包含但不限于C阶段硬化材料(C-stage material)、ABF类(Ajinomoto build-up film)材料、双马来酰亚胺-三氮杂苯(Bismaleimide Triazine,BT)树脂材料、聚酰亚胺或其类似物或其它合适的材料。所述芯材衬底所包含的树脂材料可以是由纤维增强的树脂材料，所述纤维可包含但不限于玻璃纤维或Kevlar纤维(aramid纤维)，以增强所述芯材衬底。
所述金属层106具有上表面106a、下表面106b和侧面106c。所述金属层106是直接设置于所述裸片102的背面102b。所述金属层106可帮助所述裸片102散热。所述金属层106可覆盖全部或部份的所述裸片102的背面102b，沿着所述裸片102的背面102b侧向延伸。在实施例中，所述金属层106可沿着所述裸片102的背面102b侧向延伸到所述第一介电层108的下表面108b上(介于所述裸片102的侧面102c与所述第一通孔104c的侧壁之间或延伸到所述第一通孔104c的侧壁)，由此，提供较大的散热面积。
所述金属层106包含具有热传导性质的金属材料或任何可利用电镀或无电镀形成的金属材料，如金属、金属合金、金属或金属合金分散于其中的基质。例如，所述金属层106可包含铝、铜、钛或其组合。在实施例中，所述金属层106是铜层。
所述金属层106的背面106b可进一步设置表面处理层(surface finish layer)。所述表面处理层与所述金属层106的材料可相同或不同。所述表面处理层可包含金属、金属合金、金属或金属合金分散于其中的基质。例如，所述表面处理层可包含铝、铜、钛、锡、镍和金或其组合。
所述第一图案化导电层110是设置于所述衬底104的所述第一表面104a上，并且所述第二图案化导电层112是设置于所述衬底104的所述第二表面104b上。所述第一图案化导电层110是透过所述电性互连件122与所述第二图案化导电层112电性连接。
所述防焊层(solder mask或solder resist)116是设置于所述衬底104的第二表面104b上，用来保护第二图案化导电层112与所述金属层106并界定其露出在外界的开口。所述防焊层可由感光性干膜或其它种可图案化的材料组成，例如可为但不限于聚酰亚胺。所述开口露出部份的所述第二图案化导电层，以作为外部电性连接。所述开口可具有任何形状，包含但不限于：柱状(如环形柱状、椭圆柱状、方形柱状或矩形柱状)，或非柱状(如圆锥形、漏斗形或其它锥形)。所述开孔的侧壁可具有弧度或具有纹理。
所述第一介电层108具有上表面108a和下表面108b。所述第一介电层108是设置于所述衬底104的上表面104a和所述裸片102的主动面102a上。所述第一介电层108可渗入并填满所述衬底104的第一通孔104c侧壁与所述裸片102侧面102c间的空隙。如图所示，部份的所述第一介电层108的表面可与所述金属层106的上表面106a接触。所述第一介电层108可包含聚合性介电材料或非聚合性介电材料。例如，所述第一介电层108可包含流动性较好的介电材料，其包含但不限于：液晶聚合物、预浸材(prepreg)衬底材料、ABF类(Ajinomoto build-up film)材料、树脂材料、环氧基化合物或其类似物。所述第一介电层108可具有单一树脂层或多层，如可包含由树脂组成的第一次层和由增强的树脂组成的第二次层(如使用玻璃纤维和/或Kevlar纤维增强的树脂)。在实施例中，所述第一介电层108包含预浸材材料。所述预浸材材料可由一层或两层以上的预浸材组成；或包含至少一层预浸材和至少一层树脂层。
所述第一介电层108可具有至少一个通孔，从所述第一介电层108的上表面108a延伸到所述裸片102的接垫124，露出裸片102的接垫124，和从所述第一介电层108的上表面108a延伸到所述第一图案化导电层110。所述通孔中可设有第二电性互连件120和126。在实施例中，所述第二电性互连件120和126曝露在所述第一图案化导电层110的面积小于所述第二电性互连件120和126曝露在所述介电层108的上表面108a的面积(换句话说，所述第二电性互连件的较窄处是朝向所述第一电性互连件)，由此，因所述第二电性互连件120和126与所述第一电性互连件122的几何结构相反，其可相当程度上改良所述衬底的应力，进而所述衬底的翘曲问题。另外，在实施例中，所述第二电性互连件120和126与所述第一电性互连件122可错开，由此，可进一步改良所述衬底的应力，进而改善所述衬底的翘曲问题。
所述第三图案化导电层114是设置于所述第一介电层108的上表面108a上，在所述上表面108a上实质侧向延伸。所述第三图案化导电层114是透过所述电性互连件120与所述接垫124电性连接，和透过所述电性互连件126与所述第一图案化导电层110电性连接。
所述第二介电层118是设置于所述第一介电层108上，覆盖所述第三图案化导电层114并界定其露出在外界的开口128，露出部份的所述第三图案化导电层114，以供外部电性连接。所述第二介电层118可以是防焊层(solder mask或solder resist)。例如，所述第二介电层118可由感光性干膜或其它种可图案化的材料组成，例如可为但不限于聚酰亚胺。所述第二介电层118的开口可具有任何形状，包含但不限于：柱状(如环形柱状、椭圆柱状、方形柱状或矩形柱状)，或非柱状(如圆锥形、漏斗形或其它锥形)。所述开孔的侧壁可具有弧度或具有纹理。
虽然图1绘示了第一介电层108和第二介电层118，但事实上，所述第一介电层108与所述第二介电层118可无明显分界，即其可为同一材料组成。虽然图1仅绘示了一层第一介电层108和一层第二介电层118，但在其它实施例中，第一介电层108和第二介电层118可各自由两层以上组成。
前述的电性互连件120、122和126可利用本发明领域中任何可用的材料组成，例如包含金属、金属合金、具有金属或金属合金散布于其中的材料或合适的导电材料。例如，所述电性互连件120、122和126的材料可包含铝、铜、钛或其组合。前述的第一图案化导电层110、第二图案化导电层112和第三图案化导电层114可利用本发明领域中任何可用的材料组成，例如可包含金属、金属合金、具有金属或金属合金散布于其中的材料或合适的导电材料。举例来说，前述的第一图案化导电层110、第二图案化导电层112和第三图案化导电层114可包含铝、铜、钛或其组合。所述电性互连件120、122和126与所述第一图案化导电层110、第二图案化导电层112和第三图案化导电层114的材质可相同或不同。
请参考图2，其绘示根据本发明元件嵌入式封装结构的另一实施例的剖面图。所述封装结构200在许多方面与图1所示者类似，因此，此处将仅讨论其主要不同之处。在本实施例中，所述金属层206覆盖全部或部份的所述裸片202的背面202b。另外，所述金属层206的表面可进一步设置散热片(heat sink)230，以进一步帮助散热。所述散热片230可通过粘着层232附着于所述金属层206的表面上。在实施例中，所述粘着层232为导热胶(如导热硅胶或非硅型导热胶)。
请参考图3，其绘示根据本发明元件嵌入式封装结构的另一实施例的剖面图。所述封装结构300在许多方面与图1所示者类似，因此，此处将仅讨论其主要不同之处。在本实施例中，所述金属层306覆盖全部的所述裸片的背面，并延着裸片背面、第一介电层308的表面308b侧向延伸到所述衬底304的下表面304b上与所述第二图案化导电层312接触，由此，所述裸片302所产生的热可经由所述金属层306、所述第二图案化导电层312、所述电性互连件322、所述第一图案化导电层310、所述电性互连件326和所述第三图案化导电层314导出。另外，因所述金属层306与所述裸片302和内部电路(310和314)电性连接，其也可以具有接地功用。
请参考图4，其绘示根据本发明元件嵌入式封装结构的另一实施例的剖面图。所述封装结构400在许多方面与图3所示的结构类似，因此，此处将仅讨论其主要不同之处。在本实施例中，所述金属层406的表面可进一步设置散热片(heat sink)430，以进一步帮助散热。所述散热片430可通过粘着层432附着于所述金属层406的表面上。在实施例中，所述粘着层432为导热胶(如导热硅胶或非硅型导热胶)。
请参考图5，其绘示根据本发明元件嵌入式封装结构的另一实施例的剖面图。所述封装结构500在许多方面与图1所示结构类似，因此，此处将仅讨论其主要不同之处。在本实施例中，所述封装结构500更包含第四图案化导电层536设置于所述第二介电层518上。所述第四图案化导电层536可透过电性互连件538与所述第三图案化导电层514电性连接。另外，第三介电层534可设置于所述第二介电层518上，覆盖所述第四图案化导电层536。所述第三介电层534可具有开口540，露出所述第四图案化导电层536欲与外部电性连接的部份。虽然本实施例中是以两层线路层为例(第三图案化导电层514和第四图案化导电层536)，但本发明可进一步应用于三层线路层以上。所述线路层的图案化导电层、电性互连件和介电层可与图1所示各层以相同的方式和材料形成。
请参考图6，其绘示根据本发明元件嵌入式封装结构的另一实施例的剖面图。所述封装结构600在许多方面与图1所示者类似，因此，此处将仅讨论其主要不同之处。在本实施例中，所述第二介电层618所界定出的开口可露出第三图案化导电层614作为外部电性接点的部份，例如用于与焊球连接的接垫。如图所示，焊锡或焊球642可填入所述第二介电层618所界定出的开口中，与主动元件644和被动元件646电性连接，以提供系统式封装。
请参考图7，其绘示根据本发明元件嵌入式封装结构的另一实施例的剖面图。所述封装结构700在许多方面与图5所示者类似，因此，此处将仅讨论其主要不同之处。在本实施例中，所述第三介电层734露出所述第四图案化导电层736作为外部电性接点的部份，例如用于与焊球连接的接垫。如图所示，焊锡或焊球742可填入所述第三介电层734所界定出的开口中，与主动元件744和被动元件746电性连接，以提供系统式封装。如图所示，所述第一电性互连件722和所述第二电性互连件726可错位；和所述第一电性互连件722、所述第二电性互连件726和所述第三电性互连件738可经配置以呈现扇出结构(fan-out structure)。如图所示，所述主动元件744可透过焊球742和第三电性互连件738与所述裸片702电性连接。另外，所述主动元件744也可以透过焊球742和所述第一电性互连件722、所述第二电性互连件726和所述第三电性互连件738与外部电性连接。
请参考图8，其绘示根据本发明元件嵌入式封装结构的另一实施例的剖面图。所述封装结构800在许多方面与图3所示结构类似，因此，此处将仅讨论其主要不同之处。在本实施例中，所述第二介电层818露出所述第三图案化导电层814作为外部电性接点的部份，例如用于与焊球连接的接垫。如图所示，焊锡或焊球827可填入所述第二介电层818所界定出的开口中，以便与外部电性连接。
虽然本案是按上述提供实施例和图式的方式说明本发明，但根据本发明，所述实施例和图式中所描述的每种技术特征可以互相组合。
图9A到9K绘示根据本发明的元件嵌入式封装结构的方法的实施例。以下叙述的制造半导体封装的方法也可以用于在衬底上形成多个半导体封装，每一个半导体封装可具有对应于本发明图1到8的实施例的结构。本发明方法的实施例绘示于图9A到9F中。本发明方法的另一个实施例绘示于图9A到9E、9G和9H中。本发明方法的另一个实施例绘示于图9A到9E和9G到9I中。本发明方法的另一实施例绘示于图9A到9E和9G和9J中。本发明方法的另一个实施例绘示于图9A到9E和9G到9I和9K中。本发明方法的另一个实施例绘示于图9A到9D和9L和9M中。
参考图9A，提供衬底904。在实施例中，所述衬底904可已具有第一导电箔906于第一表面904a上和第二导电箔908于其第二表面904b上。在另一实施例中，如果所述衬底本身不具有导电箔于其表面上，则所述第一导电箔906和所述第二导电箔908可视需要以层压(lamination)方式形成于所述衬底904的表面上。
参考图9B，在所述衬底904中形成从所述衬底904第一表面904a延伸到第二表面904b(或第一导电箔906到第二导电箔908)的第一通孔904c，所述第一通孔904c是用于容置裸片，故其通孔宽度和形状是根据所欲容置的裸片决定。所述第一通孔应大于等于所述裸片的尺寸。所述第一通孔可利用各种方式形成。例如，所述第一通孔可利用激光钻孔、机械钻孔方式或其它合适的方式形成；或是利用各种挖洞方式形成。例如，所述衬底的第一通孔可利用铣床、激光或冲压方式形成。在实施例中，所述第一通孔是利用冲压方式形成。所述第一通孔可为任意的形状，例如包含但不限于柱状或非柱状。柱状例如是圆柱状、椭圆柱状、方形柱状或矩形柱状。非柱状例如是圆锥状、漏斗状或其它锥状。所述第一通孔的侧面边界也可以是曲线状或大体上呈特定形状。所述开口的侧壁可具有弧度或具有纹理。在实施例中，形成所述第一通孔904c，使得底部的侧壁较靠近所述第一通孔904c顶部的侧壁较远离所述裸片。另外，所述第一导电箔906经图案化，以界定第一图案化导电层910，并且移除所述第二导电箔908，以便露出所述衬底904的第二表面904b。所述图案化过程可通过光刻和蚀刻方法达成。
参考图9C，粘性膜948配置在所述衬底904的第二表面904b上，涵盖全部或部份所述第一通孔的范围。所述粘性膜948具有粘性，使得裸片902配置于所述第一通孔中时可附着于其上。如图所示，裸片902可配置在所述第一通孔中，附着于所述粘性膜948上。所述裸片902可具有接垫924，并且其两侧与所述第一通孔的侧壁间可具有空隙904d。
参考图9D，第一介电层908是邻接配置于所述衬底904的第一表面904a上，并且覆盖所述裸片902。所述第一介电层908可实质填入所述裸片902的两侧与所述第一通孔侧壁间的空隙904d。在实施例中，所述第一介电层908可利用层压方式配置于所述衬底904的第一表面904a上。在另一实施例中，所述第一介电层908可利用任何涂布技术形成，如印刷、旋转涂布或喷洒。在实施例中，所述第一介电层908由预浸材材料形成。所述第一介电层908是形成至少一个第二通孔927，以便露出所述裸片902上的接垫924和第一图案化导电层914。所述第二通孔927可利用各种方式形成。例如，所述第二通孔927可利用光刻/蚀刻、激光钻孔、机械钻孔方式或其它可行的方式形成。在实施例中，所述第二通孔927是利用雷射钻孔方式形成。所述第二通孔927可以是任意的形状，例如包含但不限于柱状或非柱状。柱状例如是圆柱状、椭圆柱状、方形柱状或矩形柱状。非柱状例如是圆锥、漏斗或锥状。所述第二通孔927的侧面边界也可以是曲线状或大体上呈特定形状。如图所示，在配置所述第一介电层908后，因所述第一介电层908具有粘性，可帮助固定所述裸片902于所述衬底904的第一通孔904c中，所述粘性膜948便可移除。
另外，如图所示，所述衬底904是形成从所述衬底904的第二表面904b延伸到第一表面904a的第三通孔921，以便露出所述第一图案化导电层914。所述第三通孔921可利用各种方式形成。例如，所述第三通孔921可利用光刻/蚀刻、激光钻孔、机械钻孔方式或其它可行的方式形成。在实施例中，所述第三通孔921是利用雷射钻孔方式形成。在实施例中，所述第三通孔921可形成与所述第二通孔927错开。所述第三通孔921可以是任意的形状，例如包含但不限于柱状或非柱状。柱状例如是圆柱状、椭圆柱状、方形柱状或矩形柱状。非柱状例如是圆锥、漏斗或锥状。在实施例中，因所述第三通孔921是利用激光从所述衬底904的第二表面904b钻孔产生，所述第三通孔921曝露衬底第一表面904a的面积小于所述第二通孔927曝露所述第二表面904b的面积。另外，因第二通孔927与所述第三通孔921的钻孔方向不同，其相当程度可降低皆按同一方向朝衬底钻孔对衬底所产生的应力。
参考图9E，所述通孔可利用导电材料填入以形成电性互连件920、922和926。所述电性互连件920、922和926可利用任何镀膜技术形成，如无电镀和/或电镀。如图所示，形成第三图案化导电层914于所述第一介电层908的表面上和形成第二图案化导电层912于所述衬底904的第二表面904b上。所述第三图案化导电层914可包含至少一个接垫和至少一个导电迹线，其可实质上在同一步骤中形成。另外，形成金属层906于所述裸片902的背面902b上。所述金属层906可用无电镀或电镀方式形成。所述第三图案化导电层914可利用与前述第一和第二图案化导电层同样的方式形成。在实施例中，所述金属层906与所述第二图案化导电层912是可实质上在同一步骤中形成，例如皆利用电镀方式形成。
参考图9F，第二介电层918是配置于所述第一介电层908上，覆盖所述第三图案化导电层914，和填入所述第三图案化导电层914所界定出的开口。所述第二介电层918可利用形成第一介电层同样的方式形成。如图所示，所述第二介电层918可具有至少一个通孔，以便露出所述第三图案化导电层914欲电性连接的部份。所述显露的部份可以是接垫。所述通孔可利用形成图9D中的通孔同样的方式形成。所述通孔可具有前述图9D中的通孔的定义。另外，如图所示，防焊层916是设置于所述衬底904的第二表面904b上。所述防焊层916可具有开口916c，露出部份的所述第二图案化导电层912，以便作为外部电性连接，和所述金属层906。所述防焊层可由感光性干膜或其它种可图案化的材料组成，例如可为但不限于聚酰亚胺。所述开口916c可利用光刻/蚀刻、激光钻孔、机械钻孔方式或其它可行的方式形成。
参考图9G，第二介电层918是配置于所述第一介电层908上，覆盖所述第三图案化导电层914，和填入所述第三图案化导电层914所界定出的开口。所述第二介电层918可利用形成第一介电层同样的方式形成。露出第三图案化导电层914的通孔可利用导电材料填入以形成电性互连件938。所述电性互连件938可利用先前形成图9E中的电性互连件920的方式形成。如图所示，形成第四图案化导电层936于所述第二介电层918的上表面918a上。所述第四图案化导电层936可透过所述电性互连件938与所述第三图案化导电层914电性连接。所述第四图案化导电层可利用与前述第三图案化导电层同样的方式形成。所述第四图案化导电层可包含至少一个接垫和至少一个导电迹线，其可实质上在同一步骤中形成。
参考图9H，配置第三介电层934于所述第二介电层918上，覆盖所述第四图案化导电层936和填入所述第四图案化导电层936所界定出开口。所述第三介电层934可具有开口948，露出所述第四图案化导电层936欲与外界电性连接的部份，例如，可作为球垫(ball pad)，供球栅阵列(ball grid array)焊球形成于其上，或接垫，供焊线连接其它元件。所述开口948可利用形成图9D中的通孔同样的方式形成。所述第三介电层934可以是防焊层(solder mask或solder resist)。例如，所述第三介电层934可由感光性干膜组成的防焊层或其它种可图案化的材料形成，例如可以是但不限于聚酰亚胺。
另外，防焊层916是设置于所述衬底904的第二表面904b上。所述防焊层916可利用前述形成介电层的方式形成。所述防焊层916可具有开口916c，露出部份的所述第二图案化导电层912，以作为外部电性连接，和露出所述金属层906。所述防焊层可由感光性干膜或其它种可图案化的材料组成，例如可以是但不限于聚酰亚胺。所述开口916c可利用光刻/蚀刻、激光钻孔、机械钻孔方式或其它可行的方式形成。
参考图9I，在另一实施例中，散热片930是邻接设置于所述金属层906上。所述散热片930可通过粘着层932附着于所述金属层906上。在实施例中，所述粘着层932是导热胶(如导热硅胶或非硅型导热胶)，利用涂布方式形成于所述金属层906的表面上。
参考图9J，在另一实施例中，所述金属层906可形成以覆盖全部或部份所述裸片902的背面902b，和沿着所述第一介电层908的表面908b和所述衬底904的第二表面904a到所述第二图案化金属层912。所述金属层906可利用电镀或无电镀方式形成。在实施例中，所述金属层906是利用电镀形成的铜层。在实施例中，所述金属层906与所述第二图案化金属层912可在同一电镀步骤中形成。
参考图9K，在另一实施例中，将导电材料填入第三介电层918所界定出的露出第四图案化导电层936的开口以形成电性互连件942。所述电性互连件942可利用任何技术形成，如焊锡。所述电性互连件942可以是锡块或焊球942，与主动元件944和被动元件946电性连接。
参考图9L，所述通孔可利用导电材料填入以形成电性互连件920、922和926。所述电性互连件920、922和926可利用任何镀膜技术形成，如无电镀和/或电镀。如图所示，形成第三图案化导电层914于所述第一介电层908的表面上和形成第二图案化导电层912于所述衬底904的第二表面904b上。所述第三图案化导电层914可包含至少一个接垫和至少一个导电迹线，其可实质上在同一步骤中形成。另外，形成金属层906于所述裸片902的背面902b上。所述金属层906可形成以覆盖全部或部份所述裸片902的背面902b，和沿着所述第一介电层908的表面908b和所述衬底904的第二表面904a到所述第二图案化金属层912。所述金属层906可用无电镀或电镀方式形成。所述第三图案化导电层914可利用与前述第一和第二图案化导电层同样的方式形成。在实施例中，所述金属层906与所述第二图案化导电层912可实质上在同一步骤中形成，例如皆利用电镀方式形成。
参考图9M，第二介电层918是配置于所述第一介电层908上，覆盖所述第三图案化导电层914，和填入所述第三图案化导电层914所界定出的开口。所述第二介电层918可利用形成第一介电层同样的方式形成。如图所示，所述第二介电层918可具有至少一个通孔，以便露出所述第三图案化导电层914欲电性连接的部份。如图所示，焊锡或焊球927可填入所述第二介电层918所界定出的开口中，用与外部电性连接，所述显露的部份可以是接垫。所述通孔可利用光刻/蚀刻、激光钻孔、或其它可行的方式形成。在实施例中，所述通孔是利用激光钻孔方式形成。
根据以上本发明的说明可知，本发明的元件嵌入式封装结构的制造方法的实施例，是先在衬底形成上下内部连接线路，再埋置裸片于衬底中和作散热机构，此可避免先埋置裸片于衬底中和作散热机构，再在衬底形成上下内部连接线路的问题。例如，如果衬底形成上下内部连接线路的步骤的良率不佳，因裸片还未配置上去，便不会造成裸片的耗损。
图10A到10I绘示根据本发明的元件嵌入式封装结构的方法的另一实施例。以下叙述的制造半导体封装的方法也可以用于在衬底上形成多个半导体封装。
参考图10A，提供衬底1004。在实施例中，所述衬底1004可已具有第一导电箔1006于第一表面1004a上和第二导电箔1008于其第二表面1004b上。在另一实施例中，如果所述衬底本身不具有导电箔于其表面上，则所述第一导电箔1006和所述第二导电箔1008可视需要以层压(lamination)方式形成于所述衬底1004的表面上。如图所示，在所述衬底1004中形成从所述衬底1004第一表面1004a延伸到第二表面1004b(或第一导电箔1006到第二导电箔1008)的第二通孔1021。所述第二通孔1021可利用各种方式形成。例如，所述第二通孔1021可利用激光钻孔、机械钻孔方式或其它合适的方式形成；或是利用各种挖洞方式形成。在实施例中，所述第二通孔1021是利用机械钻孔方式形成。所述第二通孔1021可以是任意的形状，例如包含但不限于柱状或非柱状。柱状例如是圆柱状、椭圆柱状、方形柱状或矩形柱状。非柱状例如是圆锥状、漏斗状或其它锥状。所述第二通孔1021的侧面边界也可以是曲线状或大体上呈特定形状。所述第二通孔1021的侧壁可以具有弧度或具有纹理。另外，所述第二通孔1021可利用导电材料填入以形成电性互连件1022。所述电性互连件1022可以利用任何镀膜技术形成，如无电电镀和/或电镀。
参考图10B，图案化所述第一导电箔1006，以便形成第一图案化导电层1010，和图案化所述第二导电箔，以便形成第二图案化导电层1012。所述图案化过程可以通过光刻和蚀刻方法实现。接着，在所述衬底1004中形成从所述衬底1004第一表面1004a延伸到第二表面1004b(或第一导电箔1006到第二导电箔1008)的第一通孔1004c，所述第一通孔1004c是用于容置裸片，故其开口宽度和形状是根据所待容置的裸片决定。所述第一通孔可利用前述同样的方式形成。
参考图10C，粘性膜1048是配置在所述衬底1004的第二表面1004b上，涵盖全部或部份所述第一通孔1004c的范围。所述粘性膜1048具有粘性，使得裸片1002配置于所述第一通孔1004c中时可附着于其上。如图所示，裸片1002可配置在所述第一通孔1004c中，附着于所述粘性膜1048上。所述裸片1002可具有接垫1024，且其两侧与所述第一通孔的侧壁间可具有空隙1004d。
参考图10D，第一介电层1008是配置于所述衬底1004的第一表面1004a上，并覆盖所述裸片1002。所述第一介电层1008可实质填入所述裸片1002的两侧与所述第一通孔侧壁间的空隙1004d。在实施例中，所述第一介电层1008可利用前述的方式配置于所述衬底1004的第一表面1004a上。所述第一介电层1008是形成至少一个通孔1027，以露出所述裸片1002上的接垫1024和第一图案化导电层1014。所述通孔可利用前述的方式形成。如图所示，在配置所述第一介电层1008后，因所述第一介电层1008具有粘性，可帮助固定所述裸片1002于所述衬底1004的第一通孔1004c中，所述粘性膜1048便可移除。
参考图10E，所述通孔1027可利用导电材料填入以便形成电性互连件1020和1026。所述电性互连件1020和1026可利用前述的方式形成。如图所示，形成第三图案化导电层1014于所述第一介电层1008的表面上和形成第二图案化导电层1012于所述衬底1004的第二表面1004b上。所述第三图案化导电层1014可包含至少一个接垫和至少一个导电迹线，其可实质上在同一步骤中形成。所述第三图案化导电层1014可利用与前述第一和第二图案化导电层同样的方式形成。
参考图10F，第二介电层1018是配置于所述第一介电层1008上，覆盖所述第三图案化导电层1014，和填入所述第三图案化导电层1014所界定出的开口。所述第二介电层1018可利用前述同样的方式形成。如图所示，所述第二介电层1018可具有至少一个通孔，以便露出所述第三图案化导电层1014欲电性连接的部份。所述显露的部份可以是接垫。所述通孔可利用前述同样的方式形成。
参考图10G，露出第三图案化导电层1014的通孔可以利用导电材料填入以形成电性互连件1038。所述电性互连件1038可以利用前述的方式形成。如图所示，形成第四图案化导电层1036于所述第二介电层1018的上表面1018a上。所述第四图案化导电层1036可透过所述电性互连件1038与所述第三图案化导电层1014电性连接。所述第四图案化导电层1036可利用前述同样的方式形成。所述第四图案化导电层1036可包含至少一个接垫和至少一个导电迹线，其可实质上在同一步骤中形成。
参考图10H，配置第三介电层1034于所述第二介电层1018上，覆盖所述第四图案化导电层1036和填入所述第四图案化导电层1036所界定出开口。所述第三介电层1034可具有开口1048，露出所述第四图案化导电层1036欲电性连接的部份，例如，可作为球垫(ball pad)，供球栅阵列(ball grid array)焊球形成于其上，或接垫，供焊线连接其它元件。所述开口1048可利用前述同样的方式形成。所述第三介电层1034可以是防焊层(solder mask或solder resist)。例如，所述第三介电层1034可由感光性干膜组成的防焊层或其它种可图案化的材料形成，例如可以是但不限于聚酰亚胺。
另外，防焊层1016是设置于所述衬底1004的第二表面1004b上。所述防焊层1016可利用前述同样的方式形成。所述防焊层1016可具有开口1016c，露出部份的所述第二图案化导电层1012，以便作为外部电性连接，和具有开口1016d，以便露出所述裸片1002的背面1002b。所述防焊层可由感光性干膜或其它种可图案化的材料组成，例如可以是但不限于聚酰亚胺。所述开口1016c可利用激光钻孔、机械钻孔方式或其它可行的方式形成。
参考图10I，形成金属层1006于所述裸片1002的背面1002b上。所述金属层1006可用无电镀或电镀方式形成。在实施例中，所述散热片1030是邻接设置于所述金属层1006上。所述散热片1030可通过粘着层1032附着于所述金属层1006上。在实施例中，所述粘着层1032是导热胶(如导热硅胶或非硅型导热胶)，利用涂布方式形成于所述金属层1006的表面上。
上述实施例仅说明本发明的原理的功效，而非用于限制本发明。因此，熟悉此项技术的人士对上述实施例进行修改和变化仍不脱本发明的精神。
本案的说明书和图式仅用于阐释本发明，并非意图限制本发明的权利范围；另外，本案图式中所绘示的每种技术特征和元件仅用于使本发明领域的技术人士更了解本发明，其绘示的尺寸和其对应关系未必表示其实际关系，本发明领域的技术人士，当能根据本案所提供的权利要求书、发明说明和图式，了解本案权利要求书所涵盖的发明范围，本发明的权利范围当以本案权利要求书为准，涵盖本发明领域的技术人士从本案的说明书和图式所能合理推知的范围。

Claims (14)

1.一种元件嵌入式封装结构，其包含：
衬底，具有第一表面和相对于所述第一表面的第二表面和从所述第一表面延伸到所述第二表面的通孔；
第一电性互连件，从所述第一表面延伸到所述第二表面；
第一图案化导电层设置于所述第一表面上；
第二图案化导电层设置于所述第二表面上，透过所述第一电性互连件与所述第一图案化导电层电性连接；
至少一个裸片设置于所述通孔中，所述裸片具有一个主动面和相对于所述主动面的背面，所述裸片的背面是露出于所述衬底的第二表面；
第一介电层，填入所述裸片与所述通孔的侧壁之间的空隙并且覆盖所述裸片的所述主动面和所述衬底的第一表面；
第三图案化导电层设置于所述第一介电层的表面上，透过第二电性互连件与所述裸片电性连接；和
金属层，直接设置于所述裸片的背面上。
2.根据权利要求1所述的元件嵌入式封装结构，其中所述金属层是电镀铜层。
3.根据权利要求1所述的元件嵌入式封装结构，其中所述金属层沿着所述裸片的背面，侧向延伸到所述第二图案化导电层。
4.根据权利要求1所述的元件嵌入式封装结构，其中所述金属层与所述第二图案化导电层是同时形成。
5.根据权利要求1所述的元件嵌入式封装结构，其中所述第一电性互连件曝露在所述第一表面的面积小于所述第一电性互连件曝露在所述第二表面的面积。
6.根据权利要求1所述的元件嵌入式封装结构，其进一步包含散热片，邻接设置于所述金属层的表面上。
7.根据权利要求6所述的元件嵌入式封装结构，其进一步包含导热胶，连接所述金属层与所述散热片。
8.根据权利要求1所述的元件嵌入式封装结构，其进一步包含：
防焊层，覆盖所述第一介电层和所述第三图案化导电层，并露出部份所述第三图案化导电层；和
至少一个主动或被动元件，与所述第三图案化导电层电性连接。
9.根据权利要求1所述的元件嵌入式封装结构，其进一步包含：
第二介电层，覆盖所述第一介电层和所述第三图案化导电层，并露出部份所述第三图案化导电层；
第四图案化导电层设置于所述第二介电层的表面上，透过第三电性互连件与所述第三图案化导电层电性连接；
防焊层，覆盖所述第二介电层和所述第四图案化导电层，并露出部份所述第四图案化导电层；和
至少一个主动或被动元件，与所述第四图案化导电层电性连接。
10.根据权利要求10所述的元件嵌入式封装结构，其中所述第四图案化导电层进一步包含走线设置于所述第三电性互连件之间。
11.一种制造元件嵌入式封装结构的方法，其包含：
提供衬底，所述衬底具有上表面和下表面；
形成从所述衬底的上表面延伸到所述衬底的下表面的第一通孔；
形成电性互连件于所述第一通孔中；
形成第一图案化导电层于所述衬底的下表面上和形成第二图案化导电层于所述衬底的上表面上，其中所述第一图案化导电层与所述第二图案化导电层是透过所述电性互连件电性连接；
在所述第一通孔的侧边形成从所述衬底的上表面延伸到所述衬底的下表面的第二通孔；
配置粘性膜在所述衬底的下表面上，涵盖全部或部份的所述第二通孔范围；
配置至少一个裸片于所述第二通孔中，附着于所述粘性膜上；
提供介电层覆盖于所述裸片的所述上表面；
移除所述粘性膜，露出所述至少一个裸片的背面；和
电镀金属层于所述裸片的背面。
12.根据权利要求11所述的方法，其进一步包含机械钻孔步骤以形成所述第一通孔。
13.一种制造元件嵌入式封装结构的方法，其包含：
提供衬底，所述衬底具有上表面和下表面；
形成第一图案化导电层于所述衬底的上表面上；
形成从所述衬底的上表面延伸到所述衬底的下表面的第一通孔；
配置粘性膜在所述衬底的下表面上，涵盖全部或部份的所述第一通孔范围；
配置至少一个裸片于所述第一通孔中，附着于所述粘性膜上；
提供介电层覆盖于所述裸片的所述上表面；
移除所述粘性膜，露出所述至少一个裸片的背面；
形成从所述衬底的下表面延伸到所述衬底的上表面的第二通孔；
形成电性互连件于所述第二通孔中；
形成第二图案化导电层于所述衬底的下表面上，其中所述第一图案化导电层与所述第二图案化导电层是透过所述电性互连件电性连接；和
电镀金属层于所述裸片的背面。
14.根据权利要求13所述的方法，其进一步包含激光钻孔步骤以形成所述第一通孔。
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CN111180426A (zh) * 2019-12-31 2020-05-19 江苏长电科技股份有限公司 一种带石墨烯层散热的封装结构及其制造方法
CN111180426B (zh) * 2019-12-31 2023-09-22 江苏长电科技股份有限公司 一种带石墨烯层散热的封装结构及其制造方法

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