JP6263554B2 - 半導体チップ配置の形成方法 - Google Patents

半導体チップ配置の形成方法 Download PDF

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JP6263554B2
JP6263554B2 JP2015555644A JP2015555644A JP6263554B2 JP 6263554 B2 JP6263554 B2 JP 6263554B2 JP 2015555644 A JP2015555644 A JP 2015555644A JP 2015555644 A JP2015555644 A JP 2015555644A JP 6263554 B2 JP6263554 B2 JP 6263554B2
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chip
terminal
contact
terminal substrate
substrate
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JP2016507899A (ja
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アズダシト，ガッセム
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パック テック−パッケージング テクノロジーズ ゲーエムベーハー
パック テック−パッケージング テクノロジーズ ゲーエムベーハー
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Description

この発明は、端子基板と、端子基板上に配置された複数の半導体基板とを含み、半導体基板のコンタクト表面上に配置される端子面が、端子基板のコンタクト表面上の端子面に接続される、半導体チップ配置の形成方法に関する。
電子装置の小型化が進むにつれ、そこに用いられる電子部品の集積化の密度に関する要求も大きくなっている。これは、特に、典型的には共通のコンタクト基板を介して電気的に接触される複数のメモリチップから構成されるメモリ部品またはメモリ増設に当てはまる。
ＤＥ １９６ ２６ １２６ Ａ１から、図１において概略的に示されるようなチップ配置が公知であり、それはサンドイッチの態様で積層された配置として形成され、チップ１と中間に配置された接着層２との交互配置を含み、接着層２は、一方では、積層された配置の機械的な密着のために働き、他方では、個々のチップ１の互いからの規定された離間を可能にする。チップの積層された配置の側には、コンタクト導体基板３が設けられ、コンタクト導体基板３は、チップ１の端子面５と端子基板６との電気的なコンタクトを可能にする個々の導体経路４を備えており、端子基板６は、それぞれ、積層された配置の境界を頂部および底部において定め、その端子コンタクト７は、チップ配置の外部コンタクトのために働く。半田接続８は、チップ１の端子面５とコンタクト導体基板３の導体経路４との間の電気的コンタクトを形成するために設けられる。
図１において示されたチップ配置の複雑な構成を考慮すると、チップ配置の製造も対応して複雑であることは明らかであり、それは複数の連続する方法ステップを含み、それらは、チップ１が互いの上に配置され、接着層２によって互いから分離される、積層された配置を製造するために、およびチップ１の端子面５とコンタクト導体基板３の導体経路４との間の半田接続８を形成するために、異なるツールを用いることを必要にする。
現状技術から始めて、この発明の目的は、容易に製造することが可能であるチップ配置を提案すること、およびチップ配置の容易な製造を可能にする方法を提案することである。
前記の目的は、請求項１の特徴を有するチップ配置を形成する方法によって達成される。
この発明に従うチップ配置においては、チップは、側方縁部と平行に、それらのコンタクト表面を横断するように、端子基板のコンタクト表面に延在しており、ビアが端子基板に配置され、ビアは、外部コンタクト側上に配置された外部コンタクトを、端子基板のコンタクト表面上に内部コンタクトとして形成された端子面に接続し、側方縁部に近接して配置される半導体基板の端子面は、再溶融された半田材料デポジットによって、端子基板の内部コンタクトに接続される。この発明に従うチップ配置は、したがって、チップは単に側方縁部において端子基板に接続されるチップの列配置を可能にする。
好ましくは、端子基板の内部コンタクトとチップの端子面とは、それらが空間的角部を形成する態様で、互いに対して配置され、単に端子基板の内部コンタクト上に配置される半田材料デポジットの再溶融は、チップの端子面の濡れを可能にする。
内部コンタクトと端子面との間に形成される空間的角部は、３０°〜１５０°の角部角αを有することが好ましく、６０°〜１２０°、特に９０°の角部角αは、チップ配置の特にコンパクトな形成を可能にする。
チップの側方縁部と端子基板のコンタクト表面とが、充填隙間によって互いから離間される場合、前記充填隙間を成形材料で充填して、チップと端子基板との間に特に耐久性のある機械的な接続を形成することが可能である。
この発明に従って、端子基板と、端子基板上に配置される複数の半導体基板、特にチップとを含むチップ配置を形成する方法において、半導体基板のコンタクト表面上に配置された端子面が、端子基板のコンタクト表面上における端子面に接続され、チップは、側方縁部と平行に、それらのコンタクト表面を横断するように、端子基板のコンタクト表面に位置決めされ、側方縁部に近接して配置されるチップの端子面は、端子基板の端子面に割当てられ、端子基板の端子面は、内部コンタクトを形成し、端子基板の外部コンタクト側上に配置された外部コンタクトに、端子基板に形成されたビアによって接続され、内部コンタクトは、その後、再溶融された半田材料デポジットにより、端子面に接続される。
半田材料デポジットがチップの端子面と端子基板の内部コンタクトとの間に接続を形成するように端子基板の内部コンタクト上に配置される場合、半田材料の複数のチップへの適用は省略することが可能である。代りに、半田材料デポジットは、端子基板の内部コンタクトにのみ適用される必要があり、それは、この文脈では、さらに、その上におけるチップの配置に対して好適な位置に既に位置してもよい。
半導体基板が端子基板のコンタクト表面上に位置決めされる前に、半田材料デポジットが端子基板の内部コンタクト上に配置される場合、半田材料の適用は先に位置決めされるチップによって妨害されない。
チップは、配置ツールによって拾い上げられ、端子基板に対する所望位置に対応して方向付けられ、前記位置に保持される態様で、配置ツールによって、端子基板のコンタクト表面上に位置決めされる場合、特に有利である。
好ましくは、チップは、充填隙間がチップの側方縁部と端子基板のコンタクト表面との間において形成されるような態様で、適所に保持される。
それは、端子基板の内部コンタクトとチップの端子面とがそれらの間に角部αを形成する態様で互いに対して配置される態様でチップが位置決めされる場合、特に好まれる。
好ましくは、チップは負圧によって保持される。
端子基板の内部コンタクトとチップの端子面との間の接続の形成のための半田材料デポジットの再溶融が、チップが位置決めされている最中に起こる場合、位置決めおよび再溶融は共通の方法ステップで実行することが可能である。
好ましくは、半田材料デポジットは、配置ツールを通過するレーザ放射の衝突を受ける態様で、レーザエネルギによって再溶融される。
チップの列配置の特に容易な形成のために、端子基板のコンタクト表面上におけるチップの位置決めと、チップの端子面の端子基板の内部コンタクトへの接続とは、端子基板のコンタクト表面と平行な配置方向において、チップが次々に位置決めされ、端子基板に接続されるような態様で、連続的に起こる。
以下において、この発明は、図面の補助によってより詳細に説明され、特に、この発明に従うチップ配置を製造する方法が詳細に展開される。
現状技術に従うチップ配置を示す。 チップ配置の製造に対して好適な配置ツールの例示的な実施の形態を示す。 配置ツールの長手方向の断面図を示す。 チップ配置の端子基板を示す。 図４において示された端子基板上におけるチップの位置決めを示す。 配置方向におけるチップの端子基板上における継続的な位置決めを示す。 成形化合物を設けられたチップ配置を示す。
図４〜図７では、チップ配置１８の製造に対する連続的な方法ステップが示され、前記チップ配置１８はハウジングを形成するように成形材料１７を与えられ、初めに、図４に示されるような端子基板１２が設けられ、端子基板１２は、端子基板１２のコンタクト表面上に配置された内部コンタクト１４と端子基板１２の外部コンタクト側上に配置された外部コンタクト１５との間に導電性の接続を形成するためのビア１３を備えている。
図２および図３では、図７に示されたチップ配置１８の製造に用いられる配置ツール９が、等尺性の図示で、断面図で示される。導管の端部において、配置ツール９は、位置決め枠１１を有する窓開口部１０を有し、位置決め枠１１は、図３において示されるように、窓開口部１０におけるチップ１の正確な位置決めを可能にする。配置ツール９の導管は、位置決め枠１１に収容されるチップ１と負圧Ｕとの衝突、およびチップ１とレーザ放射Ｌとの衝突を可能にする。
負圧Ｕは、チップ１が位置決め枠１１上に固定的に保持されることを可能にする。チップ１のレーザ放射Ｌとの衝突は、チップ１のシリコン体、およびしたがって、チップ１のコンタクト表面上に配置された端子面５を、規定された方法で加熱することを可能にする。
図４が示すように、コンタクト基板１２の内部コンタクト１４には半田材料デポジット１６が与えられて、チップ１の端子面５との後のコンタクトのための準備をする。
図５および図６に示されるように、チップ１が端子基板１２の縁部に配置される状態から始めて、個々のチップ１が次いで連続的に接触され、各個々のチップ１は、配置ツール９によって負圧Ｕにより拾い上げられ、内部コンタクト１４と端子面５とが空間的角部を形成するように互いに対して配置される態様で、端子基板１２に対するその所望位置に対応して方向付けられ、この場合では、９０°の角部角αが、それぞれ、内部コンタクト１４と端子面５との間に形成される。この相対的位置では、半田材料デポジット１６の少なくとも部分的な再溶融が、レーザ放射Ｌを発するエネルギ源により起こり、短期の再溶融の後、半田材料デポジット１６によって形成された半田接続８は迅速に凝固する。
続いて、図６において示されるように、他のチップ１が継続的に配置ツール９によって次々と位置決めされ、チップ１の列配置を形成するように接触される。このプロセスでは、充填隙間２０がチップの側方縁部２１と端子基板１２のコンタクト表面との間に形成されるように、チップ１は位置決めされ、図７において示されるように、一旦チップ１の列配置が完了すると、充填隙間には、成形材料１７が充填される。
配置ツール９は、したがって、端子基板１２上におけるチップ１の規定された位置決め、および端子基板１２の内部コンタクト１４とチップ１の端子面５との間において半田接続８を形成するための半田材料デポジット１６の再溶融の両方を可能にする。このように、端子基板１２上のチップ１の配置および導電性の接続の形成は、半田材料デポジット１６の再溶融によって起こり、図１を参照して記載された現状技術における場合にあるように、２つの異なるツールによって連続的に実行される代りに、共通の方法ステップで半田接続８を形成する。
図６が示すように、すべてのチップ１は端子基板１２上に連続的に配置され、端子基板１２に導電性の態様で接続され、半田材料デポジット１６の再溶融の後、チップ１は、半田材料が半田接続８として凝固するまで、配置ツール９によって保持され、接着層２は、図１において示された現状技術における場合のように、チップ１の相対的な配置を固定するために個々のチップ１間に必要とされない。
一旦、端子基板１２上における所望数のチップ１の配置が完了すると、図７に示されるように、端子基板１２に適用される成形材料１７によって、チップ１と端子基板１２との気密封止された合成物を製造することが可能である。

Claims (9)

  1. 端子基板（１２）と、前記端子基板上に配置される複数のチップ（１）の形態の半導体基板とを含む、チップ配置（１８）を形成する方法であって、前記チップのコンタクト表面上に配置された端子面（５）が、前記端子基板のコンタクト表面上の内部コンタクトに接続され、
    窓開口部（１０）を有する配置ツール（９）を用いて、前記複数のチップのそれぞれのコンタクト表面側を、前記チップが前記配置ツールの長手軸に対して傾斜するように保持し、
    前記チップを、互いに平行に、該チップの側方縁部（２１）が前記端子基板の前記コンタクト表面と平行になるように位置決めし、かつ、前記配置ツールを、前記チップの前記側方縁部に近接して配置される前記チップの端子面が、前記端子基板の前記内部コンタクト表面上の内部コンタクト（１４）に対応して配列されるように配置し、
    前記チップを、前記チップの前記側方縁部（２１）と前記端子基板の前記コンタクト表面との間に、成形材料が充填される充填隙間が形成されように保持し、
    前記内部コンタクトは、前記端子基板の外部コンタクト側上に配置された外部コンタクト（１５）に、前記端子基板に形成されたビア（１３）によって接続され、
    その後、前記内部コンタクトを、再溶融された半田材料デポジット（１６）により、前記チップの前記端子面に接続し、
    前記半田材料デポジットの再溶融および凝固は、前記チップが前記配置ツールによって位置決めされ、保持された状態で、前記端子基板の内部コンタクトと前記チップの対応する端子面との半田接続を生じさせる、方法。
  2. 前記チップ（１）の前記端子面（５）と前記端子基板（１２）の前記内部コンタクト（１４）との間の接続の形成に先立って、前記半田材料デポジット（１６）は前記端子基板の前記内部コンタクト上に配置される、請求項１に記載の方法。
  3. 前記チップ（１）が前記端子基板の前記コンタクト表面上に位置決めされる前に、前記端子基板（１２）の前記内部コンタクト（１４）の上の前記半田材料デポジット（１６）の配置が起こる、請求項２に記載の方法。
  4. 前記端子基板（１２）の前記内部コンタクト（１４）と前記チップ（１）の前記端子面（５）とが、それらの間に角部角αを形成するような態様で、互いに対して配置されるように、前記チップ（１）の位置決めは行なわれる、請求項１〜３のいずれかに記載の方法。
  5. 前記チップ（１）は負圧によって保持される、請求項１〜４のいずれかに記載の方法。
  6. 前記端子基板（１２）の前記内部コンタクト（１４）と前記チップ（１）の前記端子面（５）との間の半田接続（８）の形成のために前記半田材料デポジット（１６）を再溶融することは、 前記チップが位置決めされている間に起こる、請求項１〜５のいずれかに記載の方法。
  7. 前記半田材料デポジット（１６）はレーザエネルギによって再溶融される、請求項１〜６のいずれかに記載の方法。
  8. 前記半田材料デポジット（１６）は、配置ツール（９）を通過するレーザ放射の衝突を受ける、請求項７に記載の方法。
  9. 前記端子基板（１２）の前記コンタクト表面上における前記チップ（１）の位置決めと、前記チップの前記端子面（５）と前記端子基板（１２）の前記内部コンタクト（１４）との接続とは、前記端子基板の前記コンタクト表面と平行な配置方向において、チップが次々に位置決めされ、前記端子基板に接続されるような態様で、連続的に起こる、請求項１〜８のいずれかに記載の方法。
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US9685423B2 (en) 2017-06-20
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EP2951861B1 (de) 2020-10-28
RU2635852C2 (ru) 2017-11-16
EP2951861A2 (de) 2015-12-09
WO2014118044A2 (de) 2014-08-07
JP2016507899A (ja) 2016-03-10
US20150364446A1 (en) 2015-12-17
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TWI539536B (zh) 2016-06-21
TW201438120A (zh) 2014-10-01

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