TW201729366A - 用於積體電路封裝的外露式可焊接散熱器 - Google Patents

用於積體電路封裝的外露式可焊接散熱器 Download PDF

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Publication number
TW201729366A
TW201729366A TW106115241A TW106115241A TW201729366A TW 201729366 A TW201729366 A TW 201729366A TW 106115241 A TW106115241 A TW 106115241A TW 106115241 A TW106115241 A TW 106115241A TW 201729366 A TW201729366 A TW 201729366A
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Taiwan
Prior art keywords
heat sink
semiconductor die
integrated circuit
conductive
circuit package
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TW106115241A
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English (en)
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奧森艾德華威廉
夏達格倫納德
奈格大衛羅伊
維特傑佛瑞金剛
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線性科技股份有限公司
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Publication of TW201729366A publication Critical patent/TW201729366A/zh

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Abstract

積體電路封裝可包含半導體晶粒、散熱器、與包覆材料。半導體晶粒可包含電子電路與對於電子電路的外露電性連結。散熱器可導熱，並可具有第一外表面以及實質上平行於第一外表面的第二外表面。第一外表面可由導熱方式附加至半導體晶粒的矽晶側的所有部分。包覆材料可為非導電性，並可完全包覆半導體晶粒與散熱器，除了散熱器的第二表面以外。散熱器的第二表面可為可焊接式，並可形成積體電路封裝外表面的部分。

Description

用於積體電路封裝的外露式可焊接散熱器
本申請案係基於申請於2014年8月1日、名為「Exposed Backside Heat-Spreader for Embedded Die Package」的美國專利臨時申請案第62/032,347號，並主張對於此臨時申請案的優先權。在此併入此臨時申請案全部內容以做為參考。
本揭示內容相關於積體電路封裝科技，包含嵌入式晶粒封裝、覆晶（flipchip）封裝、以及經配置以裝設至印刷電路板（printed circuit board；PCB）的其他類型的封裝。
積體電路封裝，諸如嵌入式晶粒封裝與覆晶封裝，可包含半導體晶粒，在半導體晶粒上製造一或更多個電子電路。半導體晶粒可為嵌入式（如在嵌入式晶粒封裝中）或附接至引線框架（如在覆晶封裝中）。可有多個半導體晶粒堆疊在單一封裝中。
這些封裝內的電子電路在作業期間內可產生大量的熱。若此熱未被快速移除，則電子電路可受損及（或）不正確地執行。因此，將此熱快速移除是重要的。
已使用了薄型橫向傳導跡線移除熱。然而，他們移除熱的速度可不如所需或所期望般的快。他們亦可對積體電路封裝的連結性要求增加複雜性。
積體電路封裝可包含半導體晶粒、散熱器、以及包覆材料。半導體晶粒可包含電子電路以及對於電子電路的外露式電性連結。散熱器可為導熱式，且具有第一外表面以及與第一外表面實質上平行的第二外表面。可將第一外表面以導熱方式附加（affix）至半導體晶粒的矽晶側的所有部分。包覆材料可為非導電式並可完全包覆半導體晶粒與散熱器，除了散熱器的第二表面以外。散熱器的第二表面可為可焊接式，並可形成積體電路封裝的外表面的部分。
在瀏覽下面對於說明性具體實施例的實施方式、附加圖式、以及申請專利範圍之後，將可清楚瞭解這些（以及其他的）部件、步驟、特徵、目標、益處、以及優點。
現在說明說明性具體實施例。可額外使用其他具體實施例（或做為替代）。可省略可為顯然或非必要的細節以節省空間，或更有效率地說明。可由額外的部件或步驟，及（或）不由所圖示說明之部件或步驟之全部，來實作一些具體實施例。
第1A圖至第1R圖圖示說明用於產生積體電路封裝（諸如嵌入式晶粒封裝）的製程範例，此封裝包含具有可焊接式表面的散熱器104b，可焊接式表面形成積體電路封裝的外表面的部分。內半導體晶粒108的矽晶側可電性及熱性地附加至散熱器104b的內表面。此封裝可讓內半導體晶粒108的矽晶側，能夠使用傳統的表面裝設科技（surface mount technology；SMT）技術來被熱性及電性地連接至印刷電路板（PCB）。附加至半導體晶粒108的散熱器104b的表面區域，可大於散熱器104b所附加的半導體晶粒108的表面的區域，以增加熱消散區域。可將散熱器104b的可焊接式表面焊接至上面裝設了積體電路封裝的PCB。第1A圖至第1R圖圖示說明的製程可使用模製互連基板（molded interconnect substrate；MIS）科技。
在第1A圖中，基底金屬層101（又可為承載層）可做為用於電鍍晶種層的基板。可由光阻膜102（例如乾膜層合光阻劑）將基底金屬層101圖案化，並處理基底金屬層101以暴露下層基底金屬區域103a、103b、與103c以供鍍覆，如第1B圖圖示說明。可例如使用雷射直接寫入、生長、以及蝕刻步驟，來完成光阻製程。
如第1C圖圖示說明，可將開放的基底金屬區域103a、103b、與103c電鍍，以提供可作為對於半導體晶粒108之電性連結的傳導區域104a、104c以及散熱器104b。傳導區域104a、104c以及散熱器104b可為任何厚度，諸如5微米與100微米之間。可使用不同的替代方法，諸如沉積製程（諸如濺射法（sputtering）），來產生傳導區域104a、104c以及散熱器104b。
這些傳導區域之一者（諸如散熱器104b），之後可被附接至半導體晶粒108的底側，並連同半導體晶粒108作為散熱器，此將於下文討論。可由導熱式材料製成散熱器104b，導熱式材料表示具有可大於2.0W/mK但不小於0.4W/mK之導熱係數的材料。
構成散熱器104b的材料亦可為傳導性與可焊接性，諸如在材料為金屬（諸如銅）時。
可提供第二互連導體層。對此，可提供第二光阻膜105，如第1D圖圖示說明。可由與光阻膜102相同的方式來處理光阻膜105（例如乾膜層合光阻劑），例如使用傳統的雷射直接寫入、生長、與蝕刻步驟。如第1E圖圖示說明，蝕刻步驟可在光阻膜105a、105b、與105c中產生開放區域106a與106b。隨後，可將這些開放區域106a與106b電鍍，以提供導電「柱」層107a與107b，如第1F圖圖示說明，導電「柱」層107a與107b可具有任何厚度，諸如75與225微米之間。隨後可移除光阻膜105a、105b、與105c，如第1G圖圖示說明。
可將半導體晶粒108的矽晶側的所有部分以黏合層109附加至散熱器104b，如第1H圖圖示說明。
半導體晶粒108可具有製造於半導體晶粒108上的、自身的互連傳導結構110a與110b。互連傳導結構110a與110b可具有任何厚度，諸如（例如）3與100微米之間。
半導體晶粒108可為任何類型。例如，半導體晶粒108可為矽、砷化鎵、互補式金氧半場效電晶體（CMOS）、雙擴散金氧半導體（DMOS）、或類比的。半導體晶粒108可具有任何尺寸。例如，半導體晶粒108可具有75與200微米之間的厚度。
黏合層109可具有任何尺寸。例如，黏合層109可延展橫越過半導體晶粒108矽晶側的整體區域。黏合層109可為熱性、導電性、與可焊接的材料，諸如Ablestik 84-1LMISR4環氧樹脂或SnSb焊料。黏合層109可具有任何厚度，諸如6與75微米之間。
隨後，可使用非導電性包覆材料111將基底金屬層101覆模（over-molded），如第1I圖圖示說明。包覆材料111可完全覆蓋並延伸過柱層107a與107b以及互連傳導結構110a與110b的頂端。例如，包覆材料111的高度可為60與600微米之間。
可將包覆材料111平坦化或磨削（ground down），以暴露柱層107a與107b以及互連傳導結構110a與110b的頂端，如第1J圖圖示說明。完全外露可需要（例如）從包覆材料111的頂端移除50與500微米之間。若互連傳導結構110a與110B的頂端不夠高，則可需要鑽入包覆材料111以接觸互連傳導結構110a與110b（諸如使用雷射）。可替代性地加入額外的傳導柱。
可在外露導體頂端上加入額外的傳導佈線層112，諸如藉由電鍍或濺射法（如第1K圖圖示說明），以將柱層107a與107b電性分別連接至互連傳導結構110a與110b。可提供光阻層113以將傳導佈線層112圖案化，如第1L圖圖示說明。
可再次使用傳統的光阻處理、生長、與蝕刻，以提供開口118a、118b、與118c，以允許蝕刻傳導佈線層112，如第1M圖圖示說明。
隨後，可使用任何適合的蝕刻製程將傳導佈線層112蝕刻，如第1N圖圖示說明。隨後可移除光阻層113a與113b，如第1O圖圖示說明。需要時可由研磨製程將經蝕刻的外露傳導佈線層112平坦化。可藉由重複上面連同第1K圖至第1N圖所說明的製程步驟一或更多次，以加入產生額外傳導層的額外圖案化。
第1O圖亦圖示說明有機可焊性保護劑（organic solderability preservative ；OSP）或抗氧化層114a與114b，可由類似的光顯影製程提供層114a與114b，以允許附接一或更多個額外的部件。額外部件可例如包含被動電路元件及（或）另一MIS科技封裝式裝置。
第1P圖圖示透過結構116a與116b（可例如為焊罩材料），將額外電性部件115電性連接至從OSP層形成的層114a與114b。可藉由重複前述步驟之一或更多者（諸如第1O圖與第1P圖圖示說明的步驟），而包含額外的焊罩、部件附接、及（或其他可圖案化式隔絕材料）。
可藉由使用非傳導性包覆材料117覆模，而完全包裝所產生的結構，如第1Q圖圖示說明。覆模可形成蓋，此蓋可具有任何厚度，諸如500與4000微米之間。
可由蝕刻選擇性移除基底金屬層101的全部或部分。第1R圖圖示說明移除基底金屬層101的部分。傳導區域104a與104c的外露表面，以及散熱器104b的外露可焊接式表面，可被使用適合的引線鍍層（lead finish）來鍍覆。可製成對於傳導區域104a與104c外露表面的焊接連結，且焊接連結可因此作為對於半導體晶粒108電路側頂端上的傳導結構110a與110b的電性連結。類似的，可製成對於散熱器104b外露可焊接式表面整體的焊接連結，因此對半導體晶粒108的矽晶側同時提供電性與熱性的連結。
為上面所說明的類型之一者的數種嵌入式積體電路封裝，可被形成於同一基板上，諸如同一基底金屬層101。隨後，可藉由去框（singulation）而獲得個別的封裝成品。
第2A圖至第2I圖圖示說明用於產生積體電路封裝（諸如嵌入式晶粒封裝）的製程的範例，此封裝包含多個佈線層並包含具有可焊接式表面的散熱器，此可焊接式表面形成積體電路封裝外表面的部分。第2A圖圖示說明在移除了光阻層113a與113b之後的第1N圖的結構。隨後，覆模步驟可由任何厚度提供非傳導性包覆材料201，諸如5與150微米之間。可使用雷射鑽孔（例如使用二氧化碳紅外線雷射），以在包覆材料201中產生對於下層佈線層112a與112b的通孔開口202a與202b，如第2C圖圖示說明。
隨後，可在包覆材料201的表面上由電鍍或濺射法填充通孔開口202a與202b，以提供傳導佈線層203（例如銅），如第2D圖圖示說明。可應用平坦化製程以確保傳導佈線層203表面的一致性。
隨後，可將傳導佈線層203圖案化並蝕刻，以提供第二互連跡線203a與203b層（由佈線層112a與112b形成第一互連層），如第2E圖圖示。可例如使用上面針對第1O圖討論的製程來應用OSP層或抗氧化層，以提供OSP或抗氧化結構204a與204b，如第2F圖圖示。隨後，可由上面在第1P圖中針對使用焊罩材料116a與116b附接電性部件115所討論的方式，使用焊罩材料210a與210b附接電性部件209，如第2G圖圖示說明。隨後，可由非傳導性包覆材料205使用覆模步驟，來包裝所產生的結構，如第2H圖圖示說明。包覆材料205可例如為1毫米至3毫米厚。如與針對第1R圖所討論者相同的方式，可藉由將基底金屬層101蝕刻以完成嵌入式積體電路封裝，如第2I圖圖示說明。圖示說明於第2H圖中的積體電路封裝的多個實例，可位於單一基底金屬層上，在此情況中每一實例被與彼此去框。
上面說明的散熱器科技可應用至其他類型的積體電路封裝。例如，可替代地由定位圖案形成預模製MIS基板，而允許凸塊晶粒（例如具有附接至接腳墊的焊接凸塊的半導體晶粒）由「覆晶」方式附接至預模製MIS基板。在凸塊晶粒附接至預模製MIS基板之後，隨後可由非傳導性包覆材料覆模所產生的結構，以包覆所產生的結構。隨後可產生開口（例如使用雷射鑽孔），以連接至半導體晶粒矽晶側以及下層基板。隨後可在包覆表面上鍍覆或濺射導體層，隨後可將導體層圖案化與平坦化（若為所需）以提供互連跡線。隨後可在互連層上提供並圖案化隔絕材料，以界定可焊接式外部墊。
第3A圖至第3B圖之每一者圖示說明不同類型的積體電路封裝的範例（諸如覆晶封裝），此封裝包含散熱器303或312，散熱器303或312之每一者具有形成積體電路封裝外表面之部分的可焊接式表面。每一積體電路封裝可包含非傳導性包覆材料301或310、半導體晶粒302或311、散熱器303或312、黏合劑304或313、內部/外部引線導體305與306或314或315（可為引線框架的部分）、以及傳導性覆晶接點307與308或316與317。部件301、302、303、304、310、311、312、與313，可相同於上面連同嵌入式晶粒封裝具體實施例所討論的對應部件。
所討論的部件、步驟、特徵、目標、益處、以及優點，僅為說明性的。這些部件、步驟、特徵、目標、益處、以及優點（以及相關的討論）均非意為由任何方式限制保護範圍。亦思及了數種其他的具體實施例。這些其他的具體實施例，包含具有較少的、額外的、及（或）不同的部件、步驟、特徵、目標、益處、及（或）優點。這些其他的具體實施例，亦包含其中由不同方式設置及（或）排序部件及（或）步驟的具體實施例。
例如，半導體晶粒可包含穿矽通孔（through-silicon via）。整合封裝亦可（或替代地）包含垂直堆疊的一或更多個額外的半導體晶粒與散熱器。
除非另外說明，否則本說明書（包含以下的申請專利範圍）所揭示的所有測量、值、額定、位置、量值、尺寸、及其他規格，皆為概略的而非準確無誤的。這些測量、值、額定、位置、量值、尺寸、及其他規格意為具有與相關功能（以及所屬技術領域之通常知識）一致的合理範圍。
在此併入本揭示內容所引用的所有文章、專利、專利申請案、以及其他刊物，以做為參考。
使用在請求項中的用語「手段（或裝置）用以（means for）……」，應被解譯為涵蓋所說明的對應結構與材料，及其均等範圍。類似的，使用在申請專利範圍中的用語「步驟用以（step for）……」，應被解譯為涵蓋所說明的對應步驟及其均等範圍。未使用這些用語的請求項，表示此請求項並非意為（且不應被解譯為）受限於這些對應結構、材料、或步驟、及其均等範圍。
保護範圍僅受限於下面的申請專利範圍。在參考本說明書以及往後的審查歷史來解譯時，此範圍意為（且應被解譯為）在與申請專利範圍所使用的語言的通常意義一致的情況下應為盡量寬廣（除非已揭示了特定的意義），並涵蓋所有結構性與功能性的均等範圍。
諸如「第一」與「第二」及類似者的相對用詞，可僅用於分辨個體或動作彼此之間，而非必須要求或隱含這些個體或動作之間的任何實際關係或次序。用詞「包含」、「包括」、及其任何變異用詞，在連同說明書或申請專利範圍中的一列元素使用時，意為指示此列表並非為排他性的，並可包含其他元素。類似的，具有綴詞「一（a）」或「一（an）」的元素，在沒有進一步的限制條件之下，並未排除相同類型的額外元素的存在。
所有申請專利範圍均非意為涵蓋不符合專利法第21條、第22條之規定的發明主題，亦不應被解譯為如此。在此對任何對於此種發明主題的無意涵蓋做出免責聲明。除了說明於此段落以外，所說明或圖示說明者均非意為（亦不應被解譯為）將任何部件、步驟、特徵、目標、益處、優點、或均等者奉獻給公眾，不論其是否記載於申請專利範圍中。
提供摘要以幫助讀者快速確認技術揭示內容的本質。應瞭解到此摘要將不用於解譯或限制申請專利範圍的範圍或意義。此外，前述實施方式中的各種特徵在各種具體實施例中被一起分組，以幫助流暢說明揭示內容。此揭示方法不應被解譯為要求所請具體實施例需要比每一請求項中明確記載的特徵還要多的特徵。相對的，如下面的申請專利範圍所反映，具有發明性的發明主題少於單一所揭示具體實施例的所有特徵。因此，在此將下面的申請專利範圍併入實施方式中，而每一請求項自身作為個別請求的發明主題。
101‧‧‧基底金屬層
102‧‧‧光阻膜
103a‧‧‧下層基底金屬區域
103b‧‧‧下層基底金屬區域
103c‧‧‧下層基底金屬區域
104a‧‧‧傳導區域
104b‧‧‧散熱器
104c‧‧‧傳導區域
105‧‧‧第二光阻膜
105a‧‧‧光阻膜
105b‧‧‧光阻膜
105c‧‧‧光阻膜
106a‧‧‧開放區域
106b‧‧‧開放區域
107a‧‧‧導電「柱」層
107b‧‧‧導電「柱」層
108‧‧‧半導體晶粒
109‧‧‧黏合層
110a‧‧‧互連傳導結構
110b‧‧‧互連傳導結構
111‧‧‧非導電性包覆材料
112‧‧‧傳導佈線層
113‧‧‧光阻層
118a‧‧‧開口
118b‧‧‧開口
118c‧‧‧開口
113a‧‧‧光阻層
113b‧‧‧光阻層
114a‧‧‧抗氧化層
114b‧‧‧抗氧化層
115‧‧‧額外電性部件
116a‧‧‧焊罩材料
116b‧‧‧焊罩材料
117‧‧‧非傳導性包覆材料
201‧‧‧非傳導性包覆材料
202a‧‧‧通孔開口
202b‧‧‧通孔開口
112a‧‧‧佈線層
112b‧‧‧佈線層
203‧‧‧傳導佈線層
203a‧‧‧第二互連跡線
203b‧‧‧第二互連跡線
204a‧‧‧抗氧化結構
204b‧‧‧抗氧化結構
209‧‧‧電性部件
210a‧‧‧焊罩材料
210b‧‧‧焊罩材料
205‧‧‧非傳導性包覆材料
301‧‧‧非傳導性包覆材料
303‧‧‧散熱器
304‧‧‧黏合劑
305‧‧‧引線導體
306‧‧‧引線導體
307‧‧‧傳導性覆晶接點
308‧‧‧傳導性覆晶接點
310‧‧‧非傳導性包覆材料
311‧‧‧半導體晶粒
312‧‧‧散熱器
313‧‧‧黏合劑
314‧‧‧引線導體
315‧‧‧引線導體
316‧‧‧傳導性覆晶接點
317‧‧‧傳導性覆晶接點
圖式係針對說明性具體實施例。這些圖式並未圖示說明所有具體實施例。可額外使用其他具體實施例（或做為替代）。可省略可為顯然或非必要的細節以節省空間，或更有效率地說明。可由額外的部件或步驟，及（或）不由所圖示說明之部件或步驟之全部，來實作一些具體實施例。在不同圖式中出現相同的編號時，此編號代表相同或類似的部件或步驟。
第1A圖至第1R圖圖示說明用於產生積體電路封裝（諸如嵌入式晶粒封裝）的製程範例，此封裝包含具有可焊接式表面的散熱器，此可焊接式表面形成積體電路封裝的外表面的部分。
第2A圖至第2I圖圖示說明用於產生積體電路封裝（諸如嵌入式晶粒封裝）的製程範例，此封裝包含多個佈線層並包含具有可焊接式表面的散熱器，此可焊接式表面形成積體電路封裝的外表面的部分。
第3A圖至第3B圖之每一者圖示說明不同類型的積體電路封裝（諸如覆晶封裝），每一封裝包含具有可焊接式表面的散熱器，此可焊接式表面形成積體電路封裝的外表面的部分。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
104a‧‧‧傳導區域
104b‧‧‧散熱器
104c‧‧‧傳導區域

Claims (17)

  1. 一種製造一積體電路封裝的方法，該積體電路封裝中包含一半導體晶粒，該半導體晶粒包含一矽晶側以及對於該半導體晶粒內之一電子電路的一或更多電性連結，該方法包含下列步驟： 將該半導體晶粒及其電性連結包覆在非導電包覆材料中；將該包覆材料雷射鑽孔以露出該積體電路封裝內的該等電性連結中之一電性連結，藉以在該包覆材料的一外表面中產生對該電性連結的一通孔開口；在該包覆材料中的該通孔開口上方電鍍或濺射以產生一傳導佈線層，該傳導佈線層從該包覆材料的該外表面到該電性連結；在該包覆步驟之前，以一導熱方式將一導熱散熱器的一第一表面附加至該半導體晶粒的該矽晶側；在該包覆步驟期間，也將該經附加散熱器包覆在該非導電包覆材料中，除了該散熱器的一第二表面以外；以及電鍍該散熱器的該第一表面至該半導體晶粒的該矽晶側。
  2. 如請求項1所述之方法，其中該散熱器的該第二表面形成該積體電路封裝的一外表面的部分。
  3. 如請求項2所述之方法，進一步包含下列步驟：將該傳導佈線層電性連接至一端點，該端點與該散熱器的該第二表面在相同平面中。
  4. 如請求項2所述之方法，其中該散熱器的該第二表面為可焊接式。
  5. 如請求項2所述之方法，其中該積體電路封裝具有一配置，該配置使得該積體電路封裝適合將該散熱器的該第二表面焊接至一電路板上的一表面，而該積體電路封裝裝設在該電路板的該表面上。
  6. 如請求項1所述之方法，其中該散熱器的該第二表面為可焊接式。
  7. 如請求項1所述之方法，進一步包含下列步驟：將該散熱器的該第一表面附加至該半導體晶粒的該矽晶側的所有部分。
  8. 如請求項1所述之方法，其中該散熱器的該第一表面具有大於該半導體晶粒之該矽晶側的表面區域。
  9. 如請求項1所述之方法，其中該散熱器的該第一及第二表面為平行的。
  10. 如請求項1所述之方法，其中該半導體晶粒具有一電路側，該電路側包含該一或更多電性連結且實質上平行於該矽晶側。
  11. 如請求項1所述之方法，進一步包含下列步驟：使用一黏合劑將該散熱器附加至該半導體晶粒的該矽晶側。
  12. 如請求項1所述之方法，其中該散熱器具導電性。
  13. 如請求項1所述之方法，進一步包含下列步驟：包覆該積體電路封裝內的至少一個額外電性部件，該至少一個額外電性部件非為該半導體晶粒的部分。
  14. 如請求項13所述之方法，進一步包含下列步驟：附接一第二導熱、可焊接式散熱器至該至少一個額外電性部件。
  15. 如請求項14所述之方法，其中該包覆步驟也包覆該第二散熱器，除了該第二散熱器的一表面以外。
  16. 如請求項1所述之方法，其中該一或更多個電性連結是電鍍的。
  17. 如請求項1所述之方法，其中該積體電路封裝包括不屬於該半導體晶粒之部分的至少一個額外電性部件，且其中該包覆步驟也包覆該至少一個額外電性部件。
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US9431319B2 (en) 2016-08-30
KR20160016629A (ko) 2016-02-15
US20160035644A1 (en) 2016-02-04
US20160260652A1 (en) 2016-09-08
CN105321900A (zh) 2016-02-10
TW201611207A (zh) 2016-03-16
US9691681B2 (en) 2017-06-27
EP2980847B1 (en) 2020-01-15
EP2980847A1 (en) 2016-02-03
TWI590396B (zh) 2017-07-01
TW201907523A (zh) 2019-02-16
KR101690051B1 (ko) 2016-12-27

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