JP6224338B2 - 半導体装置、表示装置及び半導体装置の作製方法 - Google Patents
半導体装置、表示装置及び半導体装置の作製方法 Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
Description
本実施の形態では、本発明の半導体装置の一態様について、図1(A)、(B)、(C)を用いて説明する。
本実施の形態では、実施の形態1に示す半導体装置の作製方法について、図1(B)を用いて以下説明する。また、実施の形態1で説明した機能と同様の機能を有する部分については、同様の符号を付し、その詳細な説明は省略する。
本実施の形態では、実施の形態1に示す半導体装置の変形例について、図2及び図3を用いて説明する。
従って、酸化物半導体層112のチャネル形成領域と、n型領域112aで、結晶部の結晶方向を異なる構造とすることができる。
本実施の形態では、実施の形態1、及び実施の形態3に示す半導体装置の変形例について、図4及び図5を用いて説明を行う。また、実施の形態1、及び実施の形態3で説明した機能と同様の機能を有する部分については、同様の符号を付し、その詳細な説明は省略する。
本実施の形態では、本発明の一態様の半導体装置を用いた表示装置について、図6を用いて説明を行う。
104 ゲート電極層
106 ゲート絶縁層
106a 第1の被形成面
106b 第2の被形成面
106c 第3の被形成面
108 ソース電極層
108a 第2の被形成面
110 ドレイン電極層
110a 第3の被形成面
112 酸化物半導体層
112a n型領域
113 酸化物層
114 第3の絶縁層
116 第4の絶縁層
118a 第1の絶縁層
118a1 第2の被形成面
118b 第2の絶縁層
118b1 第3の被形成面
120 トラップ準位
122,124,126,128,130,132 交差部
133 混合層
152 酸化物積層
202 基板
204 ゲート電極層
206 ゲート絶縁層
208 ソース電極層
210 ドレイン電極層
212 酸化物半導体層
212a n型領域
214 第3の絶縁層
216 第4の絶縁層
302 第1の基板
304 ゲート電極層
306 ゲート絶縁層
308 ソース電極層
310 ドレイン電極層
312 酸化物半導体層
314 第3の絶縁層
316 第4の絶縁層
318 平坦化絶縁層
320 第5の絶縁層
322 画素電極層
324 第1の配向膜
352 第2の基板
354 有色層
356 遮光層
358 有機絶縁層
360 対向電極層
362 配向膜
364 液晶層
374 画素部
376 ゲートドライバ回路部
378 ソースドライバ回路部
Claims (11)
- ゲート電極層と、
前記ゲート電極層上のゲート絶縁層と、
前記ゲート絶縁層上の絶縁層と、
前記ゲート絶縁層と前記絶縁層によって形成された凹部と、
前記凹部に沿って形成された結晶部を含む酸化物半導体層と、
前記絶縁層、及び前記酸化物半導体層上のソース電極層、及びドレイン電極層と、を有し、
前記酸化物半導体層は、チャネル形成領域と、前記ソース電極層及び前記ドレイン電極層と接するn型領域と、を有し、
前記チャネル形成領域と、前記n型領域で、前記結晶部の結晶方向が異なり、
前記絶縁層は、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、窒化シリコン膜、及び窒化酸化シリコン膜の群から選択された一からなる単層、または前記群から選択された複数の膜からなる積層である
ことを特徴とする半導体装置。 - ゲート電極層と、
前記ゲート電極層上のゲート絶縁層と、
前記ゲート絶縁層上の第1の絶縁層及び第2の絶縁層と、
前記ゲート絶縁層、前記第1の絶縁層、及び前記第2の絶縁層上の結晶部を含む酸化物半導体層と、
前記第1の絶縁層、及び前記酸化物半導体層上のソース電極層と、
前記第2の絶縁層、及び前記酸化物半導体層上のドレイン電極層と、を有し、
前記酸化物半導体層は、チャネル形成領域と、前記ソース電極層及び前記ドレイン電極層と接するn型領域と、を有し、
前記チャネル形成領域は、前記ゲート絶縁層と接する前記酸化物半導体層に位置し、
前記ゲート絶縁層が前記酸化物半導体層に接する面は、前記第1の絶縁層が前記酸化物半導体層に接する面、及び前記第2の絶縁層が前記酸化物半導体層に接する面それぞれと交差し、
前記第1の絶縁層及び前記第2の絶縁層それぞれは、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、窒化シリコン膜、及び窒化酸化シリコン膜の群から選択された一からなる単層、または前記群から選択された複数の膜からなる積層である
ことを特徴とする半導体装置。 - ゲート電極層と、
前記ゲート電極層上の凹部を有するゲート絶縁層と、
前記凹部に沿って形成された結晶部を含む酸化物半導体層と、
前記ゲート絶縁層、及び前記酸化物半導体層上のソース電極層、及びドレイン電極層と、を有し、
前記酸化物半導体層は、チャネル形成領域と、前記ソース電極層及び前記ドレイン電極層と接するn型領域と、を有し、
前記チャネル形成領域と、前記n型領域で、前記結晶部の結晶方向が異なり、
前記ゲート絶縁層は、前記ゲート電極層の上面全てに接する
ことを特徴とする半導体装置。 - ゲート電極層と、
前記ゲート電極層上の第1の被形成面、第2の被形成面、及び第3の被形成面を有するゲート絶縁層と、
前記第1の被形成面、前記第2の被形成面、及び前記第3の被形成面上の結晶部を含む酸化物半導体層と、
前記第2の被形成面上の前記酸化物半導体層に接するソース電極層と、
前記第3の被形成面上の前記酸化物半導体層に接するドレイン電極層と、を有し、
前記酸化物半導体層は、チャネル形成領域と、前記ソース電極層及び前記ドレイン電極層と接するn型領域と、を有し、
前記チャネル形成領域は、前記第1の被形成面上の前記酸化物半導体層に位置し、
前記第1の被形成面は、前記第2の被形成面及び前記第3の被形成面それぞれと交差し、
前記ゲート絶縁層は、前記ゲート電極層の上面全てに接する
ことを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記酸化物半導体層は、
少なくともインジウム(In)、亜鉛(Zn)及びM(Al、Ga、Ge、Y、Zr、Sn、La、CeまたはHfの金属)を含むIn−M−Zn酸化物で表記される酸化物である
ことを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記酸化物半導体層は、
In−Ga−Zn酸化物で表記される酸化物である
ことを特徴とする半導体装置。 - 請求項1乃至請求項6のいずれか一において、
前記結晶部は、c軸が前記酸化物半導体層の被形成面の法線ベクトルに平行な方向に揃う
ことを特徴とする半導体装置。 - 請求項1または2において、
前記酸化物半導体層は、CAAC−OSを有する
ことを特徴とする半導体装置。 - 請求項1乃至請求項8のいずれか一に記載する半導体装置を有する表示装置。
- ゲート電極層上にゲート絶縁層を形成し、
前記ゲート絶縁層上に第1の絶縁層及び第2の絶縁層を形成し、
前記ゲート絶縁層、前記第1の絶縁層、及び前記第2の絶縁層上に結晶部を含む酸化物半導体層を形成し、
前記第1の絶縁層、及び前記酸化物半導体層上にソース電極層を形成し、
前記第2の絶縁層、及び前記酸化物半導体層上にドレイン電極層を形成する半導体装置の作製方法であり、
前記酸化物半導体層は、チャネル形成領域と、前記ソース電極層及び前記ドレイン電極層と接するn型領域と、を有し、
前記チャネル形成領域は、前記ゲート絶縁層と接する前記酸化物半導体層に位置し、
前記ゲート絶縁層が前記酸化物半導体層に接する面は、前記第1の絶縁層が前記酸化物半導体層に接する面、及び前記第2の絶縁層が前記酸化物半導体層に接する面それぞれと交差し、
前記第1の絶縁層及び前記第2の絶縁層それぞれは、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、窒化シリコン膜、及び窒化酸化シリコン膜の群から選択された一からなる単層、または前記群から選択された複数の膜からなる積層である
ことを特徴とする半導体装置の作製方法。 - ゲート電極層上に、前記ゲート電極層の上面全てに接し、且つ第1の被形成面、第2の被形成面、及び第3の被形成面を有するゲート絶縁層を形成し、
前記第1の被形成面、前記第2の被形成面、及び前記第3の被形成面上に結晶部を含む酸化物半導体層を形成し、
前記第2の被形成面上の前記酸化物半導体層に接するソース電極層を形成し、
前記第3の被形成面上の前記酸化物半導体層に接するドレイン電極層を形成する半導体装置の作製方法であり、
前記酸化物半導体層は、チャネル形成領域と、前記ソース電極層及び前記ドレイン電極層と接するn型領域と、を有し、
前記チャネル形成領域は、前記第1の被形成面上の前記酸化物半導体層に位置し、
前記第1の被形成面は、前記第2の被形成面及び前記第3の被形成面それぞれと交差する
ことを特徴とする半導体装置の作製方法。
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