JP6145066B2 - 半導体素子構造を製造する方法 - Google Patents
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- H01L29/66333—Vertical insulated gate bipolar transistors
Description
例えば、パワーIGBTsまたはパワーダイオード等の、バイポーラパワー半導体素子は、他の半導体領域とのpn接合を形成する、ベース領域(通常低濃度でドープされている(lightly doped))を有している。逆電圧の印加によって上記pn接合に逆方向バイアスがかかると、上記素子は、ターンオフされる。この場合、ベース領域において、空間電荷領域が形成され、この空間電荷領域は、上記pn接合から進行して、ベース領域内に広がるにつれて、逆電圧が高くなり、ベース領域のドーピングが低くなる。
本発明の一態様は、第1及び第2の面を有する半導体基材に半導体素子構造を製造する方法であって、上記方法は、異なってドープされた、同一導電型の2つの半導体領域を製造するために、上記面の何れか1つの面を介して、その全面に渡って、半導体基材内に第1の導電型のドーパント原子を注入する、第1の注入を行う工程と、上記1つの面が部分的に露出するように、上記1つの面にマスクを製造する工程と、半導体基材において、上記面のうち1つの面から進んで、上記マスクにより露出された領域に侵食することにより、少なくともドーパント原子の注入部分を除去する工程と、上記マスクを除去する工程とを含み、上記マスクが除去される前または後に、上記面のうち1つの面を介して、半導体基材内に第1の導電型のドーパント原子を注入する第2の注入を行う、方法に関する。
図面を参照して、以下に、実施例を説明する。この場合、主な強調点は、基本原理を明らかにする点にある。したがって、図面には、この基本原理を理解するのに必要なシグナル回路素子が示されている。図面では、特に指摘しない限り、同一の参照符号は、同一の素子領域を示し、同一の意味を有するものである。
図1は、パワーIGBTの一例を示す垂直断面図である。このパワーIGBTは、第1の面(以下、表面と称する)101、及び第2の面(以下、裏面と称する)102を有する半導体基材100を備えている。表面101及び裏面102は、半導体基材100における垂直方向の範囲を規定する。横方向においては、半導体基材100は、エッジ103によって範囲が規定されている。図示した例では、エッジ103は、表面101及び裏面102に対し垂直に延びているが、表面101及び/または裏面102に対して傾斜して、延び得る(不図示)。
本記述の参考に係る一態様は、半導体基材を備えたパワーIGBTであって、上記半導体基材は、第1及び第2の面、並びにエッジを有するとともに、内側領域と、記半導体基材の横方向において該内側領域及び上記エッジに隣接するエッジ領域を有し、少なくとも1つの内側領域及び少なくとも1つのエッジ領域に配置された、第1の導電型のベース領域と、半導体基材の垂直方向において上記ベース領域に隣接して配置されている、上記第1の導電型に対し相補的な第2の導電型のエミッタ領域と、上記ベース領域に隣接して配置されている、第1の導電型のフィールド停止領域と、を備え、上記フィールド停止領域は、上記エッジ領域で第1のドーパント量を含む第1のフィールド停止区域と、上記内側領域で第2のドーパント量を含む第2のフィールド停止区域とを有し、上記第1のドーパント量は、上記第2のドーパント量よりも高くなっており、上記エミッタ領域は、上記エッジ領域の部分で取り除かれており、上記フィールド停止領域は、上記ベース領域よりも高い濃度でドープされている、パワーIGBTに関する。
Claims (8)
- 第1及び第2の面を有する半導体基材を備えたパワーIGBTを製造する方法であって、上記方法は、異なってドープされた、同一導電型の2つの半導体領域を製造するために、
上記面の何れか1つの面を介して、その全面に渡って、半導体基材内に第1の導電型のドーパント原子を注入することによって、フィールド停止区域を形成する、第1の注入を行う第1の工程と、
上記1つの面が部分的に露出するように、上記1つの面にマスクを製造する第2の工程と、
上記半導体基材において、上記1つの面から進んで、上記マスクにより露出された上記1つの面の領域に侵食することにより、上記第1の工程において注入された上記第1の導電型のドーパント原子の少なくとも一部を除去する第3の工程と、
上記マスクを除去する第4の工程とを含み、
上記第1の工程から第4の工程までは、この順に実施され、
上記第3の工程の後かつ上記第4の工程の前、または上記第4の工程の後に、上記1つの面を介して、上記半導体基材内に第1の導電型のドーパント原子を注入することによって、フィールド停止領域を形成する、第2の注入を行うことを特徴とする方法。 - 上記第3の工程の後かつ上記第4の工程の前に、上記1つの面を介して、上記半導体基材内に第2の導電型のドーパント原子を注入することによって、エミッタ領域を形成する、第3の注入を行う工程をさらに含むことを特徴とする請求項1に記載の方法。
- 上記第3の工程は、注入用の上記マスクを用いて行われることを特徴とする請求項1に記載の方法。
- 上記第2の注入により導入される上記第1の導電型のドーパント原子は、セレン原子または硫黄原子であることを特徴とする請求項1に記載の方法。
- パワーIGBTを製造する方法であって、
上記方法は、第1の注入を行う第1の工程を含んでおり、
上記第1の工程は、
第1の面を介して、半導体基材内に第1の導電型のドーパント原子を注入することによって、フィールド停止区域を形成する工程を含んでおり、
上記方法は、
上記第1の面の一領域を露出したまま、上記第1の面にマスクを製造する第2の工程と、
上記マスクにより露出された領域から進んで、上記半導体基材を浸食することにより、上記第1の工程において注入された上記第1の導電型のドーパント原子の少なくとも一部を除去する第3の工程と、
上記マスクを除去する第4の工程と、
をさらに含んでおり、
上記第1の工程から第4の工程までは、この順に実施され、
上記第3の工程の後かつ上記第4の工程の前、または上記第4の工程の後に、上記第1の面を介して、上記半導体基材内に上記第1の導電型のドーパント原子を注入することによって、フィールド停止領域を形成する、第2の注入を行うことを特徴とする方法。 - 上記第3の工程の後かつ上記第4の工程の前に、上記マスクを用いて、上記第1の面を介し、上記半導体基材内に第2の導電型のドーパント原子を注入することによって、エミッタ領域を形成する、第3の注入を行う工程をさらに含むことを特徴とする請求項5に記載の方法。
- 上記第3の工程は、注入用の上記マスクを用いて行われることを特徴とする請求項6に記載の方法。
- 上記第2の注入によって導入される上記第1の導電型のドーパント原子は、セレン原子または硫黄原子であることを特徴とする請求項7に記載の方法。
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US8466491B2 (en) * | 2011-05-12 | 2013-06-18 | Infineon Technologies Austria Ag | Semiconductor component with improved softness |
CN103650147B (zh) * | 2011-07-05 | 2016-07-06 | 三菱电机株式会社 | 半导体装置 |
US9184255B2 (en) * | 2011-09-30 | 2015-11-10 | Infineon Technologies Austria Ag | Diode with controllable breakdown voltage |
US10164043B2 (en) * | 2012-01-11 | 2018-12-25 | Infineon Technologies Ag | Semiconductor diode and method for forming a semiconductor diode |
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