JP6121501B2 - 半導体ウエハーの製造方法と低格子間酸素濃度を有する半導体デバイス - Google Patents
半導体ウエハーの製造方法と低格子間酸素濃度を有する半導体デバイス Download PDFInfo
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- JP6121501B2 JP6121501B2 JP2015199932A JP2015199932A JP6121501B2 JP 6121501 B2 JP6121501 B2 JP 6121501B2 JP 2015199932 A JP2015199932 A JP 2015199932A JP 2015199932 A JP2015199932 A JP 2015199932A JP 6121501 B2 JP6121501 B2 JP 6121501B2
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Description
また、本願は以下に記載する態様を含む。
(態様1)
基板ウエハー(100)を製造する方法であって、
第1の面(111)と前記第1の面(111)に対向する第2の面(112)とを有するデバイスウエハー(110)であって半導体材料で作られるとともに第1の厚さ(d1)を有するデバイスウエハー(110)を提供する工程と、
前記第2の面(112)における少なくとも領域(112a)内の前記デバイスウエハー(110)の酸素含有量を低減するための第1の高温処理へ前記デバイスウエハー(110)を付す工程と、
前記デバイスウエハー(110)の前記第2の面(112)をキャリヤウエハー(120)の第1の面(121)へ接着して前記キャリヤウエハー(120)へ接着される前記デバイスウエハー(110)を含む基板ウエハー(100)を形成する工程であって、前記キャリヤウエハー(120)は前記第1の面(121)に対向する第2の面(122)を有し、前記キャリヤウエハー(120)の第2の面(122)は前記基板ウエハー(100)の前記第2の面(102)を形成し、前記デバイスウエハー(110)の前記第1の面(111)は前記基板ウエハー(100)の第1の面(101)を形成する、工程と、
前記デバイスウエハー(110)の厚さを前記デバイスウエハーの前記第1の厚さ(d1)未満である第2の厚さ(d2)まで低減するために、前記デバイスウエハー(110)の前記第1の面(111)により形成される前記基板ウエハー(100)の前記第1の面(101)を処理する工程と、
前記キャリヤウエハー(120)へ接着された少なくとも前記デバイスウエハー(110)の酸素含有量を低減するための第2の高温処理へ前記基板ウエハー(100)を付す工程と、
前記第2の高温処理後に前記デバイスウエハー(110)内に少なくとも1つの半導体部品(140)を少なくとも部分的に集積化する工程と、を含む方法。
(態様2)
前記デバイスウエハー(110)を前記キャリヤウエハー(120)へ接着する前に前記デバイスウエハー(110)の前記第2の面(112)と前記キャリヤウエハー(120)の前記第1の面(121)の少なくとも一方の上に酸素障壁(114)を形成する工程をさらに含む態様1に記載の方法。
(態様3)
前記デバイスウエハー(110)を前記キャリヤウエハー(120)へ接着する前に前記キャリヤウエハー(120)を、前記キャリヤウエハー(120)の酸素含有量を低減するための第3の高温処理に付す工程をさらに含む態様1または2に記載の方法。
(態様4)
前記デバイスウエハー(110)を提供する工程は、5*10 17 /cm 3 以下、特には3*10 17 /cm 3 以下の初期格子間酸素濃度を有する前記デバイスウエハー(110)を提供する工程を含む、態様1〜3のいずれか一項に記載の方法。
(態様5)
前記デバイスウエハー(110)の前記第1の厚さ(d1)は300μm〜850μmである、態様1〜4のいずれか一項に記載の方法。
(態様6)
前記デバイスウエハー(100)の前記第2の厚さ(d2)は400未満μmである、態様1〜5のいずれか一項に記載の方法。
(態様7)
前記デバイスウエハー(110)の厚さを低減した後に前記デバイスウエハー(110)の縁(116)を処理する工程をさらに含む態様1〜6のいずれか一項に記載の方法。
(態様8)
前記半導体部品(140)を少なくとも部分的に集積化した後に前記キャリヤウエハー(120)を除去する工程をさらに含む態様1〜7のいずれか一項に記載の方法。
(態様9)
前記デバイスウエハー(110)と前記キャリヤウエハー(120)のそれぞれは少なくとも150mm(6インチ)、特には少なくとも200mm(8インチ)の直径を有する、態様1〜8のいずれか一項に記載の方法。
(態様10)
前記デバイスウエハー(110)の前記第1と第2の面(111、112)の少なくとも一方の上に酸化物層(118)を形成する工程と、
前記デバイスウエハー(110)を前記第1の高温処理に付す前に前記酸化物層(118)を除去する工程と、をさらに含む態様1〜9のいずれか一項に記載の方法。
(態様11)
前記デバイスウエハー(110)を前記キャリヤウエハー(120)へ接着する前に前記デバイスウエハー(110)の前記第2の面(112)上にエピタキシャル層(113)とドープ領域(113)の少なくとも1つを形成する工程をさらに含む態様1〜10のいずれか一項に記載の方法。
(態様12)
前記デバイスウエハー(110)を前記キャリヤウエハー(120)へ接着する前に前記キャリヤウエハー(121)の前記第1の面においてドーピング領域(125)を形成する工程をさらに含む態様1〜11のいずれか一項に記載の方法。
(態様13)
前記第1と第2の高温処理の少なくとも一方は不活性雰囲気内で1000℃〜1300℃の温度で1〜20時間行われる、態様1〜12のいずれか一項に記載の方法。
(態様14)
前記第1と第2の高温処理の少なくとも一方は酸化性雰囲気内で1100℃以下の温度で1〜20時間行われる、態様1〜13のいずれか一項に記載の方法。
(態様15)
前記キャリヤウエハーは半導体材料を含む、態様1〜14のいずれか一項に記載の方法。
(態様16)
基板ウエハー(330)を製造する方法であって、
半導体材料の1つまたは複数の単結晶インゴット(300)の酸素濃度分布を判断する工程であって、前記インゴットは特にはCZインゴットまたはMCZインゴットである、工程と、
所与の酸素閾値未満である酸素濃度を有する前記1つまたは複数の単結晶インゴット(300)の少なくとも第1の領域(301)を選択する工程と、
前記所与の閾値を越える酸素濃度を有する前記1つまたは複数の単結晶インゴット(300)の少なくとも第2の領域(302)を選択する工程と、
少なくとも第1の半導体ウエハー(310)を形成するために前記第1の領域(301)をスライスする工程と、
少なくとも第2の半導体ウエハー(320)を形成するために前記第2の領域(302)をスライスする工程と、
前記第1の半導体ウエハー(310)を前記第2の半導体ウエハー(320)へ接着する工程と、を含む方法。
(態様17)
前記酸素閾値は5*10 17 /cm 3 であり、特には3*10 17/ cm 3 以下である、態様16に記載の方法。
(態様18)
基板ウエハー(330)を製造する方法であって、
半導体材料の1つまたは複数の単結晶インゴット(300)の抵抗率分布を判断する工程であって、前記インゴットは特にはCZインゴットまたはMCZインゴットである、工程と、
所与の抵抗率範囲内の抵抗率を有する前記1つまたは複数の単結晶インゴット(300)の少なくとも第1の領域(301)を選択する工程と、
所与の抵抗率範囲外の抵抗率を有する前記1つまたは複数の単結晶インゴット(300)の少なくとも第2の領域(302)を選択する工程と、
少なくとも第1の半導体ウエハー(310)を形成するために前記第1の領域(301)をスライスする工程と、
少なくとも第2の半導体ウエハー(320)を形成するために前記第2の領域(302)をスライスする工程と、
前記第1の半導体ウエハー(310)を前記第2の半導体ウエハー(320)へ接着する工程と、を含む方法。
(態様19)
前記所与の抵抗率範囲の中心は20Ω*cm〜240Ω*cmであり、前記中心の周りの範囲は、+/−30%、好適には+/−15%、またはさらに好適には+/−8%である、態様18に記載の方法。
(態様20)
前記1つまたは複数の単結晶インゴット(300)の前記第1の領域(301)と前記第2の領域(302)は、前記第2の半導体ウエハー(320)の厚さ未満である厚さを有する前記第1の半導体ウエハー(310)を提供するためにスライスされる、態様16〜19のいずれか一項に記載の方法。
(態様21)
第1の面(211)、前記第1の面(211)に対向する第2の面(212)、厚さ(d2)を有する半導体基板(210)、特には単結晶シリコン基板と、
前記半導体基板(210)へ集積化された少なくとも1つの半導体部品と、
前記半導体基板(210)の前記第1の面(211)における第1の金属被覆(251)と、
前記半導体基板(210)の前記第2の面(212)における第2の金属被覆(252)と、を含む半導体デバイスであって、
前記半導体基板(210)は、前記第1の面(211)に対する前記厚さ(d2)の20%〜80%の位置に全体の最大値を有する前記半導体基板(210)の厚み線に沿った酸素濃度を有し、
前記全体の最大値は、前記半導体基板(210)の前記第1の面(211)と前記第2の面(212)のそれぞれにおける酸素濃度より少なくとも2倍大きい、特には少なくとも5倍大きい、半導体デバイス。
(態様22)
前記酸素濃度の前記全体の最大値は、5*10 17 /cm 3 未満、特には3*10 17 /cm 3 以下である、態様21に記載の半導体デバイス。
(態様23)
前記半導体デバイス(200)はバイポーラデバイス、特にはIGBTまたは電力用ダイオードである、態様21または22に記載の半導体デバイス。
(態様24)
前記半導体デバイス(200)はユニポーラデバイス、特にはパワーMOSFETである、態様21または22に記載の半導体デバイス。
71 初期Oi濃度
72 第1の高温処理後のOi濃度
73 第2の高温処理後の初期Oi濃度
100 基板ウエハー
101 基板ウエハーの第1の面
101p 基板ウエハーの処理済み第1の面
102 基板ウエハーの第2の面
110 デバイスウエハー
110a 初期Oi濃度を有する領域
111a/112a 低減Oi濃度を有する領域
111 デバイスウエハーの第1の面
111p デバイスウエハーの処理済み第1の面
112 デバイスウエハーの第2の面
113 エピタキシャル領域/ドーピング領域
114 障壁層/窒化物層
116 鋭い縁
117 丸い縁
118 任意選択的酸素層
119 円周方向上縁
120 キャリヤウエハー
120a 未酸化領域
121a/122a 低減Oi濃度を有する酸化物層/領域
121 キャリヤウエハーの第1の面
122 キャリヤウエハーの第2の面
125 pドープ領域
140 半導体部品
141 ドーピング領域
151 前面金属被膜
152 後面金属被膜
190 レーザ
199 凹部
200 半導体デバイス
210 デバイスウエハー/半導体基板
211 デバイスウエハー/半導体基板の第1の面
212 デバイスウエハー/半導体基板の第2の面
230 トレンチ
231 ゲート電極
232 ゲート誘電体
235 絶縁層
236 ゲートポリ
237 ゲートコンタクト
239 メサ
241 第1のドーピング領域/ソース領域
242 第2のドーピング領域/ボディ領域
243 第3のドーピング領域/ドリフト領域
244 第4のドーピング領域/電界停止領域
245 第5のドーピング領域/エミッタ領域
251 前面金属被膜/ソース金属被覆
252 後面金属被膜/エミッタ金属被覆
253 ソースコンタクト
300 単結晶インゴット
301 第1の領域
302 第2の領域
310 第1の半導体ウエハー/デバイスウエハー
320 第2の半導体ウエハー/キャリヤウエハー
330 基板ウエハー
Claims (15)
- 基板ウエハー(100)を製造する方法であって、
第1の面(111)と前記第1の面(111)に対向する第2の面(112)とを有するデバイスウエハー(110)であって半導体材料で作られるとともに第1の厚さ(d1)を有するデバイスウエハー(110)を提供する工程と、
前記第2の面(112)における少なくとも領域(112a)内の前記デバイスウエハー(110)の酸素含有量を低減するための第1の高温処理へ前記デバイスウエハー(110)を付す工程と、
前記デバイスウエハー(110)の前記第2の面(112)をキャリヤウエハー(120)の第1の面(121)へ接着して前記キャリヤウエハー(120)へ接着される前記デバイスウエハー(110)を含む基板ウエハー(100)を形成する工程であって、前記キャリヤウエハー(120)は前記第1の面(121)に対向する第2の面(122)を有し、前記キャリヤウエハー(120)の第2の面(122)は前記基板ウエハー(100)の前記第2の面(102)を形成し、前記デバイスウエハー(110)の前記第1の面(111)は前記基板ウエハー(100)の第1の面(101)を形成する、工程と、
前記デバイスウエハー(110)の厚さを前記デバイスウエハーの前記第1の厚さ(d1)未満である第2の厚さ(d2)まで低減するために、前記デバイスウエハー(110)の前記第1の面(111)により形成される前記基板ウエハー(100)の前記第1の面(101)を処理する工程と、
前記キャリヤウエハー(120)へ接着された少なくとも前記デバイスウエハー(110)の酸素含有量を低減するための第2の高温処理へ前記基板ウエハー(100)を付す工程と、
前記第2の高温処理後に前記デバイスウエハー(110)内に少なくとも1つの半導体部品(140)を少なくとも部分的に集積化する工程と、を含み、前記デバイスウエハー(110)は、磁気的CZ法を含むCZ法により形成されたインゴットからカットされる、方法。 - 前記デバイスウエハー(110)を前記キャリヤウエハー(120)へ接着する前に前記デバイスウエハー(110)の前記第2の面(112)と前記キャリヤウエハー(120)の前記第1の面(121)の少なくとも一方の上に酸素障壁(114)を形成する工程をさらに含む請求項1に記載の方法。
- 前記デバイスウエハー(110)を前記キャリヤウエハー(120)へ接着する前に前記キャリヤウエハー(120)を、前記キャリヤウエハー(120)の酸素含有量を低減するための第3の高温処理に付す工程をさらに含む請求項1または2に記載の方法。
- 前記デバイスウエハー(110)を提供する工程は、5*1017/cm3以下の初期格子間酸素濃度を有する前記デバイスウエハー(110)を提供する工程を含む、請求項1〜3のいずれか一項に記載の方法。
- 前記デバイスウエハー(110)の前記第1の厚さ(d1)は300μm〜850μmである、請求項1〜4のいずれか一項に記載の方法。
- 前記デバイスウエハー(100)の前記第2の厚さ(d2)は400未満μmである、請求項1〜5のいずれか一項に記載の方法。
- 前記デバイスウエハー(110)の厚さを低減した後に前記デバイスウエハー(110)の縁(116)を処理する工程をさらに含む請求項1〜6のいずれか一項に記載の方法。
- 前記半導体部品(140)を少なくとも部分的に集積化した後に前記キャリヤウエハー(120)を除去する工程をさらに含む請求項1〜7のいずれか一項に記載の方法。
- 前記デバイスウエハー(110)と前記キャリヤウエハー(120)のそれぞれは少なくとも150mm(6インチ)の直径を有する、請求項1〜8のいずれか一項に記載の方法。
- 前記デバイスウエハー(110)の前記第1と第2の面(111、112)の少なくとも一方の上に酸化物層(118)を形成する工程と、
前記デバイスウエハー(110)を前記第1の高温処理に付す前に前記酸化物層(118)を除去する工程と、をさらに含む請求項1〜9のいずれか一項に記載の方法。 - 前記デバイスウエハー(110)を前記キャリヤウエハー(120)へ接着する前に前記デバイスウエハー(110)の前記第2の面(112)上にエピタキシャル層(113)とドープ領域(113)の少なくとも1つを形成する工程をさらに含む請求項1〜10のいずれか一項に記載の方法。
- 前記デバイスウエハー(110)を前記キャリヤウエハー(120)へ接着する前に前記キャリヤウエハー(121)の前記第1の面においてドーピング領域(125)を形成する工程をさらに含む請求項1〜11のいずれか一項に記載の方法。
- 前記第1と第2の高温処理の少なくとも一方は不活性雰囲気内で1000℃〜1300℃の温度で1〜20時間行われる、請求項1〜12のいずれか一項に記載の方法。
- 前記第1と第2の高温処理の少なくとも一方は酸化性雰囲気内で1100℃以下の温度で1〜20時間行われる、請求項1〜13のいずれか一項に記載の方法。
- 前記キャリヤウエハーは半導体材料を含む、請求項1〜14のいずれか一項に記載の方法。
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