JP6095674B2 - バッテリ保護回路のパッケージモジュール - Google Patents
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M2010/4271—Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Description
120:プロテクションIC
100:積層チップ
n1:第1ノード
n2:第2ノード
A1:第1内部連結端子領域
A2:外部連結端子領域
A3:素子領域
A4:チップ領域
A5:第2内部連結端子領域
Claims (6)
- バッテリ保護回路のパッケージモジュールにおいて、
両縁部にそれぞれ備えられ、ベアセルが内蔵されたバッテリカンと連結される第1内部連結端子及び第2内部連結端子がそれぞれ配される第1内部連結端子領域及び第2内部連結端子領域と、
前記第1内部連結端子領域に隣接し、複数の外部連結端子が配される外部連結端子領域と、
前記バッテリ保護回路を構成する複数の受動素子が配される素子領域と、前記素子領域に隣接し、前記バッテリ保護回路を構成するプロテクション(protection)IC及びデュアルFETチップが配されるチップ領域とが、前記外部連結端子領域と前記第2内部連結端子領域との間に配される保護回路領域と、を備えて、
上部面には、前記複数の外部連結端子が露出され、下部面には、前記第1内部連結端子及び前記第2内部連結端子が露出されるようにパッケージングされた構造を有し、
前記チップ領域には、共通ドレイン構造の第1FET及び第2FETを内蔵した前記デュアルFETチップと、過放電及び過充電の動作を制御する前記プロテクションICとが上下積層されるか、互いに隣接して配され、
前記素子領域には、少なくとも1つの抵抗及び少なくとも1つのキャパシタを含む複数の受動素子が、複数の導電性ラインのうち少なくとも2本の導電性ラインを互いに連結する構造でそれぞれ配され、
前記バッテリ保護回路のパッケージモジュールは、前記チップ領域に備えられて、前記プロテクションIC及び前記デュアルFETチップが装着されるダイパッドと、
前記素子領域に備えられて、前記複数の導電性ラインを構成する第1ないし第6受動素子用リードと、
前記外部連結端子領域に備えられて、前記複数の外部連結端子を構成する第1ないし第3外部連結端子用リードと、
前記複数の外部連結端子用リードのうち、第1外部連結端子用リードから延びて構成され、前記第1内部連結端子領域に備えられて、前記第1内部連結端子を構成する第1内部連結端子用リードと、
前記第2内部連結端子領域に備えられて、前記第2内部連結端子を構成する第2内部連結端子用リードと、を備えるリードフレーム構造を有することを特徴とする、バッテリ保護回路のパッケージモジュール。 - 前記プロテクションICで過放電状態で前記第1FETをオフさせるための放電遮断信号を出力する放電遮断信号出力端子DOは、前記第1FETのゲート端子とワイヤボンディングを通じて電気的に連結され、
前記プロテクションICで過充電状態で前記第2FETをオフさせるための充電遮断信号を出力する充電遮断信号出力端子COは、前記第2FETのゲート端子とワイヤボンディングを通じて電気的に連結され、
前記プロテクションICの基準電圧端子VSSは、前記第1FETのソース端子または第3受動素子用リードとワイヤボンディングを通じて電気的に連結され、
第1受動素子用リードは、前記第1外部連結端子用リードとワイヤボンディングを通じて電気的に連結され、
第2受動素子用リードは、前記プロテクションICで充電電圧及び放電電圧が印加される電圧印加端子VDDとワイヤボンディングを通じて電気的に連結され、
第3受動素子用リードは、前記第1FETのソース端子及び前記第2内部連結端子用リードとワイヤボンディングを通じて電気的に連結され、
第4受動素子用リードは、第2外部連結端子用リードとワイヤボンディングを通じて電気的に連結され、
第5受動素子用リードは、前記第2FETのソース端子及び第3外部連結端子用リードとワイヤボンディングを通じて電気的に連結され、
第6受動素子用リードは、前記プロテクションICで充放電状態を感知するための感知端子V−とワイヤボンディングを通じて電気的に連結され、
前記複数の受動素子のうち、第1抵抗は、前記第1受動素子用リードと前記第2受動素子用リードとの間に配され、
前記複数の受動素子のうち、第2抵抗は、前記第5受動素子用リードと前記第6受動素子用リードとの間に配され、
前記複数の受動素子のうち、サージ保護回路を構成する第3抵抗は、前記第4受動素子用リードと前記第5受動素子用リードとの間に配され、
前記複数の受動素子のうち、第1キャパシタは、前記第2受動素子用リードと前記第3受動素子用リードとの間に配され、
前記複数の受動素子のうち、第2キャパシタは、前記第3受動素子用リードと前記第5受動素子用リードとの間に配され、
前記複数の受動素子のうち、前記サージ保護回路を構成するバリスタ(varistor)は、前記第3抵抗と並列に構成されて、前記第4受動素子用リードと前記第5受動素子用リードとの間に配されることを特徴とする請求項1に記載のバッテリ保護回路のパッケージモジュール。 - バッテリ保護回路のパッケージモジュールにおいて、
両縁部にそれぞれ備えられ、ベアセルが内蔵されたバッテリカンと連結される第1内部連結端子及び第2内部連結端子がそれぞれ配される第1内部連結端子領域及び第2内部連結端子領域と、
前記第1内部連結端子領域に隣接し、複数の外部連結端子が配される外部連結端子領域と、
前記バッテリ保護回路を構成する複数の受動素子が配される素子領域と、前記素子領域に隣接し、前記バッテリ保護回路を構成するプロテクション(protection)IC及びデュアルFETチップが配されるチップ領域とが、前記外部連結端子領域と前記第2内部連結端子領域との間に配される保護回路領域と、を備えて、
上部面には、前記複数の外部連結端子が露出され、下部面には、前記第1内部連結端子及び前記第2内部連結端子が露出されるようにパッケージングされた構造を有し、
前記チップ領域には、共通ドレイン構造の第1FET及び第2FETを内蔵した前記デュアルFETチップと、過放電及び過充電の動作を制御する前記プロテクションICとが上下積層されるか、互いに隣接して配され、
前記素子領域には、少なくとも1つの抵抗及び少なくとも1つのキャパシタを含む複数の受動素子が、複数の導電性ラインのうち少なくとも2本の導電性ラインを互いに連結する構造でそれぞれ配され、
前記バッテリ保護回路のパッケージモジュールは、PCB基板、セラミック基板及びプラスチック基板のうちから選択された何れか1つのベース基板上に、前記チップ領域、前記素子領域、前記外部連結端子領域、前記第1内部連結端子領域及び第2内部連結端子領域が配される構造を有し、
前記外部連結端子領域には、第1ないし第3外部連結端子が配され、
前記第1内部連結端子領域には、第1外部連結端子から延びて構成される第1内部連結端子が配され、
前記第2内部連結端子領域には、第2内部連結端子が配され、
前記素子領域には、前記外部連結端子領域、前記チップ領域及び前記第2内部連結端子領域のうちから選択された少なくとも1つの領域まで延設された第1ないし第6の導電性ラインが配される構造を有し、
前記プロテクションICで過放電状態で前記第1FETをオフさせるための放電遮断信号を出力する放電遮断信号出力端子DOは、前記第1FETのゲート端子とワイヤボンディングを通じて電気的に連結され、
前記プロテクションICで過充電状態で前記第2FETをオフさせるための充電遮断信号を出力する充電遮断信号出力端子COは、前記第2FETのゲート端子とワイヤボンディングを通じて電気的に連結され、
前記プロテクションICの基準電圧端子VSSは、前記第1FETのソース端子または第3導電性ラインとワイヤボンディングを通じて電気的に連結され、
第1導電性ラインは、前記素子領域から前記外部連結端子領域まで延設されて、前記第1外部連結端子と電気的に連結され、
第2導電性ラインは、前記素子領域から前記チップ領域まで延設されて、前記プロテクションICで充電電圧及び放電電圧が印加される電圧印加端子VDDとワイヤボンディングを通じて電気的に連結され、
第3導電性ラインは、前記素子領域から前記チップ領域及び前記第2内部連結端子領域まで延設されて、前記第1FETのソース端子及び前記第2内部連結端子と電気的に連結され、
第4導電性ラインは、前記素子領域から前記外部連結端子領域まで延設されて、第2外部連結端子と電気的に連結され、
第5導電性ラインは、前記素子領域から前記外部連結端子領域まで延設されて、前記第2FETのソース端子及び第3外部連結端子と電気的に連結され、
第6導電性ラインは、前記素子領域から前記チップ領域まで延びて、前記プロテクションICで充放電状態を感知するための感知端子V−と電気的に連結され、
前記複数の受動素子のうち、第1抵抗は、前記第1導電性ラインと前記第2導電性ラインとの間に配され、
前記複数の受動素子のうち、第2抵抗は、前記第5導電性ラインと前記第6導電性ラインとの間に配され、
前記複数の受動素子のうち、サージ保護回路を構成する第3抵抗は、前記第4導電性ラインと前記第5導電性ラインとの間に配され、
前記複数の受動素子のうち、第1キャパシタは、前記第2導電性ラインと前記第3導電性ラインとの間に配され、
前記複数の受動素子のうち、第2キャパシタは、前記第3導電性ラインと前記第5導電性ラインとの間に配され、
前記複数の受動素子のうち、前記サージ保護回路を構成するバリスタは、前記第3抵抗と並列に構成されて、前記第4導電性ラインと前記第5導電性ラインとの間に配されることを特徴とする、バッテリ保護回路のパッケージモジュール。 - 前記第3導電性ラインと前記第2内部連結端子との間には、バッテリパックの過電流を抑制するためのPTC(Positive Temperature Coefficient thermistor(resistor))素子またはヒューズ(fuse)がさらに配されることを特徴とする請求項3に記載のバッテリ保護回路のパッケージモジュール。
- 前記バッテリ保護回路のパッケージモジュールは、前記バッテリカンに装着されてバッテリパックを構成することを特徴とする請求項3に記載のバッテリ保護回路のパッケージモジュール。
- 前記バッテリ保護回路のパッケージモジュールは、前記バッテリカンと結合されてバッテリパックを構成する上部ケース構造を有することを特徴とする請求項3に記載のバッテリ保護回路のパッケージモジュール。
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KR10-2011-0103628 | 2011-10-11 | ||
PCT/KR2012/006593 WO2013055026A1 (ko) | 2011-10-11 | 2012-08-20 | 배터리 보호회로의 패키지 모듈 |
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