JP6088200B2 - 時間分割多重化された多重ポートメモリ - Google Patents

時間分割多重化された多重ポートメモリ Download PDF

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Publication number
JP6088200B2
JP6088200B2 JP2012232813A JP2012232813A JP6088200B2 JP 6088200 B2 JP6088200 B2 JP 6088200B2 JP 2012232813 A JP2012232813 A JP 2012232813A JP 2012232813 A JP2012232813 A JP 2012232813A JP 6088200 B2 JP6088200 B2 JP 6088200B2
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Prior art keywords
port
memory
memory access
access request
clock signal
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Japanese (ja)
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JP2013097792A5 (enExample
JP2013097792A (ja
Inventor
ルイス デイビッド
ルイス デイビッド
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Altera Corp
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Altera Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
JP2012232813A 2011-10-28 2012-10-22 時間分割多重化された多重ポートメモリ Expired - Fee Related JP6088200B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/284,721 2011-10-28
US13/284,721 US8806259B2 (en) 2011-10-28 2011-10-28 Time division multiplexed multiport memory implemented using single-port memory elements

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017018597A Division JP6293322B2 (ja) 2011-10-28 2017-02-03 時間分割多重化された多重ポートメモリ

Publications (3)

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JP2013097792A JP2013097792A (ja) 2013-05-20
JP2013097792A5 JP2013097792A5 (enExample) 2015-09-24
JP6088200B2 true JP6088200B2 (ja) 2017-03-01

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JP2012232813A Expired - Fee Related JP6088200B2 (ja) 2011-10-28 2012-10-22 時間分割多重化された多重ポートメモリ
JP2017018597A Active JP6293322B2 (ja) 2011-10-28 2017-02-03 時間分割多重化された多重ポートメモリ

Family Applications After (1)

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JP2017018597A Active JP6293322B2 (ja) 2011-10-28 2017-02-03 時間分割多重化された多重ポートメモリ

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US (2) US8806259B2 (enExample)
EP (1) EP2587486B1 (enExample)
JP (2) JP6088200B2 (enExample)
CN (1) CN103093808B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9230622B2 (en) * 2012-11-30 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Simultaneous two/dual port access on 6T SRAM
US10289186B1 (en) * 2013-10-31 2019-05-14 Maxim Integrated Products, Inc. Systems and methods to improve energy efficiency using adaptive mode switching
CN104318952B (zh) * 2014-09-30 2017-11-10 西安紫光国芯半导体有限公司 Dram中一种减少电压端口的电路及方法
US10430215B1 (en) * 2015-06-25 2019-10-01 Cadence Design Systems, Inc. Method and system to transfer data between hardware emulator and host workstation
JP6637872B2 (ja) * 2016-10-28 2020-01-29 ルネサスエレクトロニクス株式会社 マルチポートメモリおよび半導体装置
US10652912B2 (en) * 2018-04-30 2020-05-12 Microchip Technology Incorporated Smart radio arbiter with conflict resolution based on timing predictability
US11194942B1 (en) * 2018-12-06 2021-12-07 Cadence Design Systems, Inc. Emulation system supporting four-state for sequential logic circuits
CN110059036B (zh) * 2019-04-15 2022-04-26 西安微电子技术研究所 一种存储体内部多异步接口访问控制装置及方法
KR102767986B1 (ko) * 2020-02-17 2025-02-14 에스케이하이닉스 주식회사 반도체장치

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JPS63285648A (ja) * 1987-05-19 1988-11-22 Fujitsu Ltd メモリアクセス調停方式
US4796232A (en) 1987-10-20 1989-01-03 Contel Corporation Dual port memory controller
US4937781A (en) 1988-05-13 1990-06-26 Dallas Semiconductor Corporation Dual port ram with arbitration status register
US5047921A (en) 1989-01-31 1991-09-10 International Business Machines Corporation Asynchronous microprocessor random access memory arbitration controller
US5708850A (en) * 1994-07-27 1998-01-13 Sony Corporation Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock
JPH0944395A (ja) * 1995-08-02 1997-02-14 Fujitsu Ltd 非同期アクセス調停方式
US5768211A (en) 1996-07-31 1998-06-16 Cypress Semiconductor Corporation Multi-port arbitration for high performance width expansion
TW451215B (en) * 1998-06-23 2001-08-21 Motorola Inc Pipelined dual port integrated circuit memory
US5973985A (en) 1998-08-11 1999-10-26 Stmicroelectronics, Inc. Dual port SRAM cell having pseudo ground line or pseudo power line
US6388939B1 (en) 1999-09-30 2002-05-14 Cypress Semiconductor Corp. Dual port sram
US6118689A (en) 1999-10-27 2000-09-12 Kuo; James B. Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
US6816955B1 (en) 2000-09-29 2004-11-09 Cypress Semiconductor Corp. Logic for providing arbitration for synchronous dual-port memory
US6751151B2 (en) 2001-04-05 2004-06-15 International Business Machines Corporation Ultra high-speed DDP-SRAM cache
US6606275B2 (en) 2001-08-23 2003-08-12 Jeng-Jye Shau High performance semiconductor memory devices
US7421559B1 (en) * 2003-12-18 2008-09-02 Cypress Semiconductor Corporation Apparatus and method for a synchronous multi-port memory
KR100560948B1 (ko) 2004-03-31 2006-03-14 매그나칩 반도체 유한회사 6 트랜지스터 듀얼 포트 에스램 셀
JP2006252656A (ja) * 2005-03-10 2006-09-21 Nec Electronics Corp マルチポートメモリ装置
JP4914034B2 (ja) 2005-06-28 2012-04-11 セイコーエプソン株式会社 半導体集積回路
JP4425243B2 (ja) * 2005-10-17 2010-03-03 Ｏｋｉセミコンダクタ株式会社 半導体記憶装置
US7603496B2 (en) * 2006-01-23 2009-10-13 Arm Limited Buffering data during data transfer through a plurality of channels
JP5038657B2 (ja) * 2006-06-26 2012-10-03 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US7564738B2 (en) 2006-08-11 2009-07-21 Freescale Semiconductor, Inc. Double-rate memory
KR100846386B1 (ko) * 2006-09-21 2008-07-15 주식회사 하이닉스반도체 멀티포트 메모리 장치
JP2009238351A (ja) * 2008-03-28 2009-10-15 Oki Semiconductor Co Ltd デュアルポート半導体記憶装置およびそのタイミング発生装置
JP2010044821A (ja) * 2008-08-11 2010-02-25 Hitachi Ulsi Systems Co Ltd 半導体装置とメモリマクロ

Also Published As

Publication number Publication date
EP2587486A2 (en) 2013-05-01
US20130111253A1 (en) 2013-05-02
CN103093808B (zh) 2017-03-01
US8806259B2 (en) 2014-08-12
CN103093808A (zh) 2013-05-08
JP6293322B2 (ja) 2018-03-14
US9298211B2 (en) 2016-03-29
JP2017091577A (ja) 2017-05-25
EP2587486A3 (en) 2013-06-12
US20140331074A1 (en) 2014-11-06
JP2013097792A (ja) 2013-05-20
EP2587486B1 (en) 2019-09-11

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