JP2013097792A5 - - Google Patents

Download PDF

Info

Publication number
JP2013097792A5
JP2013097792A5 JP2012232813A JP2012232813A JP2013097792A5 JP 2013097792 A5 JP2013097792 A5 JP 2013097792A5 JP 2012232813 A JP2012232813 A JP 2012232813A JP 2012232813 A JP2012232813 A JP 2012232813A JP 2013097792 A5 JP2013097792 A5 JP 2013097792A5
Authority
JP
Japan
Prior art keywords
access request
clock signal
memory access
port
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012232813A
Other languages
English (en)
Japanese (ja)
Other versions
JP6088200B2 (ja
JP2013097792A (ja
Filing date
Publication date
Priority claimed from US13/284,721 external-priority patent/US8806259B2/en
Application filed filed Critical
Publication of JP2013097792A publication Critical patent/JP2013097792A/ja
Publication of JP2013097792A5 publication Critical patent/JP2013097792A5/ja
Application granted granted Critical
Publication of JP6088200B2 publication Critical patent/JP6088200B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2012232813A 2011-10-28 2012-10-22 時間分割多重化された多重ポートメモリ Expired - Fee Related JP6088200B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/284,721 2011-10-28
US13/284,721 US8806259B2 (en) 2011-10-28 2011-10-28 Time division multiplexed multiport memory implemented using single-port memory elements

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017018597A Division JP6293322B2 (ja) 2011-10-28 2017-02-03 時間分割多重化された多重ポートメモリ

Publications (3)

Publication Number Publication Date
JP2013097792A JP2013097792A (ja) 2013-05-20
JP2013097792A5 true JP2013097792A5 (enExample) 2015-09-24
JP6088200B2 JP6088200B2 (ja) 2017-03-01

Family

ID=47225945

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2012232813A Expired - Fee Related JP6088200B2 (ja) 2011-10-28 2012-10-22 時間分割多重化された多重ポートメモリ
JP2017018597A Active JP6293322B2 (ja) 2011-10-28 2017-02-03 時間分割多重化された多重ポートメモリ

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2017018597A Active JP6293322B2 (ja) 2011-10-28 2017-02-03 時間分割多重化された多重ポートメモリ

Country Status (4)

Country Link
US (2) US8806259B2 (enExample)
EP (1) EP2587486B1 (enExample)
JP (2) JP6088200B2 (enExample)
CN (1) CN103093808B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9230622B2 (en) * 2012-11-30 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Simultaneous two/dual port access on 6T SRAM
US10289186B1 (en) * 2013-10-31 2019-05-14 Maxim Integrated Products, Inc. Systems and methods to improve energy efficiency using adaptive mode switching
CN104318952B (zh) * 2014-09-30 2017-11-10 西安紫光国芯半导体有限公司 Dram中一种减少电压端口的电路及方法
US10430215B1 (en) * 2015-06-25 2019-10-01 Cadence Design Systems, Inc. Method and system to transfer data between hardware emulator and host workstation
JP6637872B2 (ja) * 2016-10-28 2020-01-29 ルネサスエレクトロニクス株式会社 マルチポートメモリおよび半導体装置
US10652912B2 (en) * 2018-04-30 2020-05-12 Microchip Technology Incorporated Smart radio arbiter with conflict resolution based on timing predictability
US11194942B1 (en) * 2018-12-06 2021-12-07 Cadence Design Systems, Inc. Emulation system supporting four-state for sequential logic circuits
CN110059036B (zh) * 2019-04-15 2022-04-26 西安微电子技术研究所 一种存储体内部多异步接口访问控制装置及方法
KR102767986B1 (ko) * 2020-02-17 2025-02-14 에스케이하이닉스 주식회사 반도체장치

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63285648A (ja) * 1987-05-19 1988-11-22 Fujitsu Ltd メモリアクセス調停方式
US4796232A (en) 1987-10-20 1989-01-03 Contel Corporation Dual port memory controller
US4937781A (en) 1988-05-13 1990-06-26 Dallas Semiconductor Corporation Dual port ram with arbitration status register
US5047921A (en) 1989-01-31 1991-09-10 International Business Machines Corporation Asynchronous microprocessor random access memory arbitration controller
US5708850A (en) * 1994-07-27 1998-01-13 Sony Corporation Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock
JPH0944395A (ja) * 1995-08-02 1997-02-14 Fujitsu Ltd 非同期アクセス調停方式
US5768211A (en) 1996-07-31 1998-06-16 Cypress Semiconductor Corporation Multi-port arbitration for high performance width expansion
TW451215B (en) * 1998-06-23 2001-08-21 Motorola Inc Pipelined dual port integrated circuit memory
US5973985A (en) 1998-08-11 1999-10-26 Stmicroelectronics, Inc. Dual port SRAM cell having pseudo ground line or pseudo power line
US6388939B1 (en) 1999-09-30 2002-05-14 Cypress Semiconductor Corp. Dual port sram
US6118689A (en) 1999-10-27 2000-09-12 Kuo; James B. Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
US6816955B1 (en) 2000-09-29 2004-11-09 Cypress Semiconductor Corp. Logic for providing arbitration for synchronous dual-port memory
US6751151B2 (en) 2001-04-05 2004-06-15 International Business Machines Corporation Ultra high-speed DDP-SRAM cache
US6606275B2 (en) 2001-08-23 2003-08-12 Jeng-Jye Shau High performance semiconductor memory devices
US7421559B1 (en) * 2003-12-18 2008-09-02 Cypress Semiconductor Corporation Apparatus and method for a synchronous multi-port memory
KR100560948B1 (ko) 2004-03-31 2006-03-14 매그나칩 반도체 유한회사 6 트랜지스터 듀얼 포트 에스램 셀
JP2006252656A (ja) * 2005-03-10 2006-09-21 Nec Electronics Corp マルチポートメモリ装置
JP4914034B2 (ja) 2005-06-28 2012-04-11 セイコーエプソン株式会社 半導体集積回路
JP4425243B2 (ja) * 2005-10-17 2010-03-03 Ｏｋｉセミコンダクタ株式会社 半導体記憶装置
US7603496B2 (en) * 2006-01-23 2009-10-13 Arm Limited Buffering data during data transfer through a plurality of channels
JP5038657B2 (ja) * 2006-06-26 2012-10-03 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US7564738B2 (en) 2006-08-11 2009-07-21 Freescale Semiconductor, Inc. Double-rate memory
KR100846386B1 (ko) * 2006-09-21 2008-07-15 주식회사 하이닉스반도체 멀티포트 메모리 장치
JP2009238351A (ja) * 2008-03-28 2009-10-15 Oki Semiconductor Co Ltd デュアルポート半導体記憶装置およびそのタイミング発生装置
JP2010044821A (ja) * 2008-08-11 2010-02-25 Hitachi Ulsi Systems Co Ltd 半導体装置とメモリマクロ

Similar Documents

Publication Publication Date Title
JP2013097792A5 (enExample)
JP2017513116A5 (enExample)
WO2012068486A3 (en) Load/store circuitry for a processing cluster
US9715464B2 (en) Direct memory access descriptor processing
WO2012109631A3 (en) Remote core operations in a multi-core computer
JP2008512785A5 (enExample)
EP2778890A3 (en) Storage device assisted data de-duplication
WO2008113647A3 (en) Shared disk clones
JP2013521579A5 (enExample)
WO2012161777A3 (en) Multi-phase resume from hibernate
JP2014510963A5 (enExample)
WO2014146027A3 (en) Data bus inversion memory circuitry, configuration and operation
WO2010051621A8 (en) Bridge device having a virtual page buffer
GB201209506D0 (en) Querying performance data on a parallel computer system having compute nodes
JP2011512585A5 (enExample)
EP2309396A3 (en) Hardware assisted inter-processor communication
MX2015017630A (es) Almacenamiento estructurado por registro, sin memoria de retencion para metodos de acceso multiple.
WO2012038829A3 (en) Low latency first-in-first-out (fifo) buffer
JP2015506042A5 (enExample)
WO2011094133A3 (en) High utilization multi-partitioned serial memory
JP2017504086A5 (enExample)
US20100049936A1 (en) Memory access control device and control method thereof
EP2587486A3 (en) Time division multiplexed multiport memory
CN105094743A (zh) 一种先进先出数据缓存器及其进行时延控制的方法
JP2016519447A5 (enExample)