CN103093808B - 时分多路复用多端口存储器 - Google Patents

时分多路复用多端口存储器 Download PDF

Info

Publication number
CN103093808B
CN103093808B CN201210421421.2A CN201210421421A CN103093808B CN 103093808 B CN103093808 B CN 103093808B CN 201210421421 A CN201210421421 A CN 201210421421A CN 103093808 B CN103093808 B CN 103093808B
Authority
CN
China
Prior art keywords
port
memory
memory access
access request
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210421421.2A
Other languages
English (en)
Chinese (zh)
Other versions
CN103093808A (zh
Inventor
D·刘易斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of CN103093808A publication Critical patent/CN103093808A/zh
Application granted granted Critical
Publication of CN103093808B publication Critical patent/CN103093808B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
CN201210421421.2A 2011-10-28 2012-10-29 时分多路复用多端口存储器 Active CN103093808B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/284,721 2011-10-28
US13/284,721 US8806259B2 (en) 2011-10-28 2011-10-28 Time division multiplexed multiport memory implemented using single-port memory elements

Publications (2)

Publication Number Publication Date
CN103093808A CN103093808A (zh) 2013-05-08
CN103093808B true CN103093808B (zh) 2017-03-01

Family

ID=47225945

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210421421.2A Active CN103093808B (zh) 2011-10-28 2012-10-29 时分多路复用多端口存储器

Country Status (4)

Country Link
US (2) US8806259B2 (enExample)
EP (1) EP2587486B1 (enExample)
JP (2) JP6088200B2 (enExample)
CN (1) CN103093808B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9230622B2 (en) * 2012-11-30 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Simultaneous two/dual port access on 6T SRAM
US10289186B1 (en) * 2013-10-31 2019-05-14 Maxim Integrated Products, Inc. Systems and methods to improve energy efficiency using adaptive mode switching
CN104318952B (zh) * 2014-09-30 2017-11-10 西安紫光国芯半导体有限公司 Dram中一种减少电压端口的电路及方法
US10430215B1 (en) * 2015-06-25 2019-10-01 Cadence Design Systems, Inc. Method and system to transfer data between hardware emulator and host workstation
JP6637872B2 (ja) * 2016-10-28 2020-01-29 ルネサスエレクトロニクス株式会社 マルチポートメモリおよび半導体装置
US10652912B2 (en) * 2018-04-30 2020-05-12 Microchip Technology Incorporated Smart radio arbiter with conflict resolution based on timing predictability
US11194942B1 (en) * 2018-12-06 2021-12-07 Cadence Design Systems, Inc. Emulation system supporting four-state for sequential logic circuits
CN110059036B (zh) * 2019-04-15 2022-04-26 西安微电子技术研究所 一种存储体内部多异步接口访问控制装置及方法
KR102767986B1 (ko) * 2020-02-17 2025-02-14 에스케이하이닉스 주식회사 반도체장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708850A (en) * 1994-07-27 1998-01-13 Sony Corporation Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock
US7421559B1 (en) * 2003-12-18 2008-09-02 Cypress Semiconductor Corporation Apparatus and method for a synchronous multi-port memory

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63285648A (ja) * 1987-05-19 1988-11-22 Fujitsu Ltd メモリアクセス調停方式
US4796232A (en) 1987-10-20 1989-01-03 Contel Corporation Dual port memory controller
US4937781A (en) 1988-05-13 1990-06-26 Dallas Semiconductor Corporation Dual port ram with arbitration status register
US5047921A (en) 1989-01-31 1991-09-10 International Business Machines Corporation Asynchronous microprocessor random access memory arbitration controller
JPH0944395A (ja) * 1995-08-02 1997-02-14 Fujitsu Ltd 非同期アクセス調停方式
US5768211A (en) 1996-07-31 1998-06-16 Cypress Semiconductor Corporation Multi-port arbitration for high performance width expansion
TW451215B (en) * 1998-06-23 2001-08-21 Motorola Inc Pipelined dual port integrated circuit memory
US5973985A (en) 1998-08-11 1999-10-26 Stmicroelectronics, Inc. Dual port SRAM cell having pseudo ground line or pseudo power line
US6388939B1 (en) 1999-09-30 2002-05-14 Cypress Semiconductor Corp. Dual port sram
US6118689A (en) 1999-10-27 2000-09-12 Kuo; James B. Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
US6816955B1 (en) 2000-09-29 2004-11-09 Cypress Semiconductor Corp. Logic for providing arbitration for synchronous dual-port memory
US6751151B2 (en) 2001-04-05 2004-06-15 International Business Machines Corporation Ultra high-speed DDP-SRAM cache
US6606275B2 (en) 2001-08-23 2003-08-12 Jeng-Jye Shau High performance semiconductor memory devices
KR100560948B1 (ko) 2004-03-31 2006-03-14 매그나칩 반도체 유한회사 6 트랜지스터 듀얼 포트 에스램 셀
JP2006252656A (ja) 2005-03-10 2006-09-21 Nec Electronics Corp マルチポートメモリ装置
JP4914034B2 (ja) 2005-06-28 2012-04-11 セイコーエプソン株式会社 半導体集積回路
JP4425243B2 (ja) * 2005-10-17 2010-03-03 Ｏｋｉセミコンダクタ株式会社 半導体記憶装置
US7603496B2 (en) * 2006-01-23 2009-10-13 Arm Limited Buffering data during data transfer through a plurality of channels
JP5038657B2 (ja) * 2006-06-26 2012-10-03 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US7564738B2 (en) 2006-08-11 2009-07-21 Freescale Semiconductor, Inc. Double-rate memory
KR100846386B1 (ko) * 2006-09-21 2008-07-15 주식회사 하이닉스반도체 멀티포트 메모리 장치
JP2009238351A (ja) * 2008-03-28 2009-10-15 Oki Semiconductor Co Ltd デュアルポート半導体記憶装置およびそのタイミング発生装置
JP2010044821A (ja) * 2008-08-11 2010-02-25 Hitachi Ulsi Systems Co Ltd 半導体装置とメモリマクロ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708850A (en) * 1994-07-27 1998-01-13 Sony Corporation Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock
US7421559B1 (en) * 2003-12-18 2008-09-02 Cypress Semiconductor Corporation Apparatus and method for a synchronous multi-port memory

Also Published As

Publication number Publication date
US8806259B2 (en) 2014-08-12
US9298211B2 (en) 2016-03-29
EP2587486A2 (en) 2013-05-01
JP6293322B2 (ja) 2018-03-14
EP2587486B1 (en) 2019-09-11
US20140331074A1 (en) 2014-11-06
CN103093808A (zh) 2013-05-08
US20130111253A1 (en) 2013-05-02
JP6088200B2 (ja) 2017-03-01
JP2017091577A (ja) 2017-05-25
JP2013097792A (ja) 2013-05-20
EP2587486A3 (en) 2013-06-12

Similar Documents

Publication Publication Date Title
CN103093808B (zh) 时分多路复用多端口存储器
US7533222B2 (en) Dual-port SRAM memory using single-port memory cell
JP4493116B2 (ja) 読み取り／書き込みアドレスバスを有するランダムアクセスメモリ並びに同メモリへの書き込み及び同メモリからの読み取り方法
US8867303B2 (en) Memory arbitration circuitry
US20010010655A1 (en) Method and system for accessing rows in multiple memory banks within an integrated circuit
JP2007525766A (ja) マルチポートメモリシステムにおける衝突検出
CN100547681C (zh) 存储器装置及在存储器装置中读取数据的方法
US6259648B1 (en) Methods and apparatus for implementing pseudo dual port memory
JP4456687B2 (ja) ランダムアクセスメモリ並びに、同メモリへの書込み及び同メモリからの読出し方法
US8773928B2 (en) Command latency systems and methods
JP4685997B2 (ja) パイプラインド・デュアル・ポート集積回路メモリ
JP2005523536A (ja) シングルポートメモリ装置へのアクセスを実行する方法、メモリアクセス装置、集積回路装置、および集積回路装置を使用する方法
US7405995B2 (en) Semiconductor storage device
JP2001035155A (ja) パイプレジスタ及びそれを備えた半導体メモリ素子
US9501407B1 (en) First-in-first-out memory with dual memory banks
JP2008004218A (ja) 半導体集積回路装置
US8971145B2 (en) Synchronous multiple port memory with asynchronous ports
US8848480B1 (en) Synchronous multiple port memory with asynchronous ports
CN104376870B (zh) 预测及避免亚稳态的存储器仲裁电路系统及其方法
TWI777847B (zh) 虛擬靜態隨機存取記憶體

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant