JP6058664B2 - 低応力ビア - Google Patents

低応力ビア Download PDF

Info

Publication number
JP6058664B2
JP6058664B2 JP2014522989A JP2014522989A JP6058664B2 JP 6058664 B2 JP6058664 B2 JP 6058664B2 JP 2014522989 A JP2014522989 A JP 2014522989A JP 2014522989 A JP2014522989 A JP 2014522989A JP 6058664 B2 JP6058664 B2 JP 6058664B2
Authority
JP
Japan
Prior art keywords
component
metal
substrate
conductive
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014522989A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014526149A5 (enExample
JP2014526149A (ja
Inventor
イリヤス モハメド
イリヤス モハメド
ベルガセム ハーバ
ベルガセム ハーバ
キプリアン ウゾ
キプリアン ウゾ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera LLC filed Critical Tessera LLC
Publication of JP2014526149A publication Critical patent/JP2014526149A/ja
Publication of JP2014526149A5 publication Critical patent/JP2014526149A5/ja
Application granted granted Critical
Publication of JP6058664B2 publication Critical patent/JP6058664B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2014522989A 2011-07-29 2012-07-26 低応力ビア Active JP6058664B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/193,814 2011-07-29
US13/193,814 US8816505B2 (en) 2011-07-29 2011-07-29 Low stress vias
PCT/US2012/048288 WO2013019541A2 (en) 2011-07-29 2012-07-26 Low-stress vias

Publications (3)

Publication Number Publication Date
JP2014526149A JP2014526149A (ja) 2014-10-02
JP2014526149A5 JP2014526149A5 (enExample) 2015-09-10
JP6058664B2 true JP6058664B2 (ja) 2017-01-11

Family

ID=46634544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014522989A Active JP6058664B2 (ja) 2011-07-29 2012-07-26 低応力ビア

Country Status (5)

Country Link
US (4) US8816505B2 (enExample)
JP (1) JP6058664B2 (enExample)
KR (1) KR101928320B1 (enExample)
TW (1) TWI538147B (enExample)
WO (1) WO2013019541A2 (enExample)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9258907B2 (en) 2012-08-09 2016-02-09 Lockheed Martin Corporation Conformal 3D non-planar multi-layer circuitry
KR101975541B1 (ko) * 2012-09-03 2019-05-07 에스케이하이닉스 주식회사 반도체 메모리 소자의 ｔｓｖ 구조 및 그 테스트 방법
US9076785B2 (en) 2012-12-11 2015-07-07 Invensas Corporation Method and structures for via substrate repair and assembly
US9123780B2 (en) 2012-12-19 2015-09-01 Invensas Corporation Method and structures for heat dissipating interposers
EP3467809B1 (en) 2013-03-12 2021-07-21 Arizona Board of Regents, a Body Corporate of the State of Arizona acting for and on behalf of Arizona State University Image processing of dendritic structures used in tags as physical unclonable function for anti-counterfeiting
DE102013204337A1 (de) * 2013-03-13 2014-09-18 Siemens Aktiengesellschaft Trägerbauteil mit einem Halbleiter-Substrat für elektronische Bauelemente und Verfahren zu dessen Herstellung
US8772745B1 (en) 2013-03-14 2014-07-08 Lockheed Martin Corporation X-ray obscuration film and related techniques
US9832887B2 (en) 2013-08-07 2017-11-28 Invensas Corporation Micro mechanical anchor for 3D architecture
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
EP2908337B1 (en) 2014-02-12 2025-11-12 ams AG Semiconductor device with a thermally stable bump contact on a TSV and method of producing such a semiconductor device
US10847442B2 (en) * 2014-02-24 2020-11-24 Micron Technology, Inc. Interconnect assemblies with through-silicon vias and stress-relief features
US9596768B2 (en) * 2014-03-04 2017-03-14 Qualcomm Incorporated Substrate with conductive vias
US9299572B2 (en) 2014-03-07 2016-03-29 Invensas Corporation Thermal vias disposed in a substrate without a liner layer
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
JP2016066705A (ja) * 2014-09-25 2016-04-28 イビデン株式会社 プリント配線板およびその製造方法
US10123410B2 (en) 2014-10-10 2018-11-06 Lockheed Martin Corporation Fine line 3D non-planar conforming circuit
WO2016073910A1 (en) 2014-11-07 2016-05-12 Arizona Board Of Regents On Behalf Of Arizona State University Information coding in dendritic structures and tags
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9812359B2 (en) 2015-06-08 2017-11-07 Globalfoundries Inc. Thru-silicon-via structures
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10130302B2 (en) * 2016-06-29 2018-11-20 International Business Machines Corporation Via and trench filling using injection molded soldering
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10049981B2 (en) * 2016-09-08 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Through via structure, semiconductor device and manufacturing method thereof
JP6808460B2 (ja) * 2016-11-29 2021-01-06 キヤノン株式会社 半導体装置及びその製造方法
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US9881867B1 (en) * 2017-01-19 2018-01-30 Nanya Technology Corporation Conductive connection structure having stress buffer layer
US10325839B2 (en) 2017-04-06 2019-06-18 International Business Machines Corporation Reduction of stress in via structure
US10204873B2 (en) * 2017-05-08 2019-02-12 Infineon Technologies Americas Corp. Breakable substrate for semiconductor die
EP3639188A4 (en) 2017-06-16 2021-03-17 Arizona Board of Regents on behalf of Arizona State University POLARIZED SCANNING OF DENDRITIC IDENTIFICATORS
JP7009111B2 (ja) 2017-08-17 2022-01-25 キヤノン株式会社 半導体装置及びその製造方法
CN112154538A (zh) 2018-03-30 2020-12-29 申泰公司 导电过孔及其制造方法
US11152294B2 (en) * 2018-04-09 2021-10-19 Corning Incorporated Hermetic metallized via with improved reliability
US11598015B2 (en) 2018-04-26 2023-03-07 Arizona Board Of Regents On Behalf Of Arizona State University Fabrication of dendritic structures and tags
US20190357364A1 (en) * 2018-05-17 2019-11-21 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With Only Partially Filled Thermal Through-Hole
KR20210064266A (ko) 2018-09-20 2021-06-02 재단법인 공업기술연구원 얇은 유리 상의 유리-관통 비아를 위한 구리 금속화
US11760682B2 (en) 2019-02-21 2023-09-19 Corning Incorporated Glass or glass ceramic articles with copper-metallized through holes and processes for making the same
WO2021067330A2 (en) * 2019-09-30 2021-04-08 Samtec, Inc. Electrically conductive vias and methods for producing same
KR102776287B1 (ko) * 2020-01-06 2025-03-07 삼성전기주식회사 인쇄회로기판
KR102423664B1 (ko) * 2020-12-31 2022-07-20 엘지디스플레이 주식회사 표시모듈, 및 이를 포함하는 표시장치와 전자기기
KR20240012398A (ko) * 2021-05-25 2024-01-29 소니 세미컨덕터 솔루션즈 가부시키가이샤 반도체 패키지 및 전자 기기
EP4420017A4 (en) 2021-10-18 2025-02-05 Arizona Board of Regents on behalf of Arizona State University AUTHENTICATION OF IDENTIFIERS BY LIGHT SCATTERING
KR20230080214A (ko) 2021-11-29 2023-06-07 삼성전자주식회사 비아 구조물을 포함하는 반도체 소자
US20230298971A1 (en) * 2022-03-18 2023-09-21 Intel Corporation Microelectronic structure including conductive polymer in trenches of a core substrate, and method of making same
CN115394789A (zh) * 2022-08-24 2022-11-25 京东方科技集团股份有限公司 显示基板及其制备方法

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2003007370A1 (ja) * 2001-07-12 2004-11-04 株式会社日立製作所 配線ガラス基板およびその製造方法ならびに配線ガラス基板に用いられる導電性ペーストおよび半導体モジュールならびに配線基板および導体形成方法
US20030011173A1 (en) * 2001-07-16 2003-01-16 Shall Harold D. Folding fishing cart
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
US6848177B2 (en) * 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6993840B2 (en) * 2002-07-18 2006-02-07 Canon Kabushiki Kaisha Manufacturing method of liquid jet head
US7060619B2 (en) * 2003-03-04 2006-06-13 Infineon Technologies Ag Reduction of the shear stress in copper via's in organic interlayer dielectric material
JP3891292B2 (ja) 2003-05-19 2007-03-14 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004349593A (ja) * 2003-05-26 2004-12-09 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US8372757B2 (en) * 2003-10-20 2013-02-12 Novellus Systems, Inc. Wet etching methods for copper removal and planarization in semiconductor processing
US7276787B2 (en) 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
JP4850392B2 (ja) * 2004-02-17 2012-01-11 三洋電機株式会社 半導体装置の製造方法
JP4387269B2 (ja) * 2004-08-23 2009-12-16 株式会社テクニスコ ビアが形成されたガラス基板及びビアの形成方法
US20060043534A1 (en) 2004-08-26 2006-03-02 Kirby Kyle K Microfeature dies with porous regions, and associated methods and systems
US7329948B2 (en) * 2004-10-15 2008-02-12 International Business Machines Corporation Microelectronic devices and methods
US7674726B2 (en) * 2004-10-15 2010-03-09 Asm International N.V. Parts for deposition reactors
JP4443379B2 (ja) * 2004-10-26 2010-03-31 三洋電機株式会社 半導体装置の製造方法
TWI303864B (en) * 2004-10-26 2008-12-01 Sanyo Electric Co Semiconductor device and method for making the same
US7741714B2 (en) 2004-11-02 2010-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure with stress-buffering layer capping interconnection metal layer
JP4891235B2 (ja) * 2005-06-01 2012-03-07 パナソニック株式会社 回路基板とその製造方法及びこれを用いた電子部品
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7528006B2 (en) 2005-06-30 2009-05-05 Intel Corporation Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion
US7863187B2 (en) * 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7262134B2 (en) * 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
WO2007029337A1 (ja) * 2005-09-09 2007-03-15 Fujitsu Limited データ損失を低減するアドホック系ネットワーク装置
US7410884B2 (en) * 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7855438B2 (en) 2006-09-19 2010-12-21 Infineon Technologies Ag Deep via construction for a semiconductor device
US20080094455A1 (en) * 2006-10-20 2008-04-24 Samsung Electronics Co., Ltd. Inkjet printhead heater and method of manufacture
EP2575166A3 (en) 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US7902069B2 (en) * 2007-08-02 2011-03-08 International Business Machines Corporation Small area, robust silicon via structure and process
JP2009094235A (ja) 2007-10-05 2009-04-30 Fujikura Ltd 半導体装置及びその製造方法
US8486823B2 (en) * 2008-03-07 2013-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming through via
US20090297879A1 (en) * 2008-05-12 2009-12-03 Texas Instruments Incorporated Structure and Method for Reliable Solder Joints
WO2009144643A1 (en) 2008-05-30 2009-12-03 Nxp B.V. Thermo-mechanical stress in semiconductor wafers
JP2010003796A (ja) * 2008-06-19 2010-01-07 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2010010324A (ja) 2008-06-26 2010-01-14 Toshiba Corp 半導体装置及び半導体装置の製造方法
KR100997788B1 (ko) 2008-06-30 2010-12-02 주식회사 하이닉스반도체 반도체 패키지
JP5242282B2 (ja) * 2008-07-31 2013-07-24 株式会社東芝 半導体装置とその製造方法
US8344513B2 (en) * 2009-03-23 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier for through-silicon via
KR20110050957A (ko) 2009-11-09 2011-05-17 삼성전자주식회사 반도체 소자의 관통 비아 콘택 및 그 형성 방법
US20110204517A1 (en) 2010-02-23 2011-08-25 Qualcomm Incorporated Semiconductor Device with Vias Having More Than One Material
US8329575B2 (en) * 2010-12-22 2012-12-11 Applied Materials, Inc. Fabrication of through-silicon vias on silicon wafers
US8723049B2 (en) 2011-06-09 2014-05-13 Tessera, Inc. Low-stress TSV design using conductive particles
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias

Also Published As

Publication number Publication date
US20140332981A1 (en) 2014-11-13
US9659858B2 (en) 2017-05-23
US20130026645A1 (en) 2013-01-31
US20170250132A1 (en) 2017-08-31
TW201320287A (zh) 2013-05-16
KR101928320B1 (ko) 2018-12-12
JP2014526149A (ja) 2014-10-02
WO2013019541A2 (en) 2013-02-07
KR20140050693A (ko) 2014-04-29
US9214425B2 (en) 2015-12-15
US10283449B2 (en) 2019-05-07
US20150325498A1 (en) 2015-11-12
WO2013019541A4 (en) 2013-05-30
WO2013019541A3 (en) 2013-04-18
US8816505B2 (en) 2014-08-26
TWI538147B (zh) 2016-06-11

Similar Documents

Publication Publication Date Title
JP6058664B2 (ja) 低応力ビア
JP6067679B2 (ja) 多孔質基板内のビア
JP6143851B2 (ja) 応力が低減されたｔｓｖ及びインタポーザ構造体
JP5941983B2 (ja) 導電性粒子を用いた低応力なシリコン貫通ビアのデザイン
US20140159249A1 (en) Method and structures for via substrate repair and assembly

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150724

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150724

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160224

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160524

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20161107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161207

R150 Certificate of patent or registration of utility model

Ref document number: 6058664

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250