JP6046262B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6046262B2 JP6046262B2 JP2015537502A JP2015537502A JP6046262B2 JP 6046262 B2 JP6046262 B2 JP 6046262B2 JP 2015537502 A JP2015537502 A JP 2015537502A JP 2015537502 A JP2015537502 A JP 2015537502A JP 6046262 B2 JP6046262 B2 JP 6046262B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- semiconductor device
- bonding
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 57
- 239000010410 layer Substances 0.000 claims description 255
- 229910000679 solder Inorganic materials 0.000 claims description 29
- 239000011229 interlayer Substances 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- 239000002344 surface layer Substances 0.000 description 12
- 239000004642 Polyimide Substances 0.000 description 7
- 238000001816 cooling Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000036413 temperature sense Effects 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- -1 titanium or tungsten Chemical compound 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
<構成>
図1は、本実施形態に関する表面電極をはんだ接合した半導体装置の断面図である。なお、図7と同一の構成要素には同一の符号を付し、適宜説明を省略する。
図2は、本実施形態の他の態様に関する半導体装置の断面図である。なお、図7と同一の構成要素には同一の符号を付し、適宜説明を省略する。
図3は、本実施形態の他の態様に関する半導体装置の断面図である。なお、図7と同一の構成要素には同一の符号を付し、適宜説明を省略する。
本実施形態によれば、半導体装置が、第1導電型(n型)のドリフト層12と、ドリフト層12上のうちの部分領域である第1領域(IGBT領域)に形成された、ゲート構造と、IGBT領域およびドリフト層12上のうちの他の領域である第2領域(ダイオード領域)を覆って配置された、表面電極2と、表面電極2上に部分的に形成された接合層40と、接合層40上に形成されたはんだ層3と、はんだ層3上に配置されたリードフレーム1とを備える。
<構成>
図4は、本実施形態に関する表面電極をはんだ接合した半導体装置の断面図である。なお、図7と同一の構成要素には同一の符号を付し、適宜説明を省略する。
図5は、本実施形態の他の態様に関する半導体装置の断面図である。なお、図7と同一の構成要素には同一の符号を付し、適宜説明を省略する。
本実施形態によれば、半導体装置が、n型のドリフト層12と、ドリフト層12上に形成された、p型のベース層10と、ベース層10表層からドリフト層12内に達して形成された溝13と、溝13の側面および底面に沿って形成されたゲート絶縁膜8と、溝13内のゲート絶縁膜8の内側に形成されたゲート電極9と、ベース層10表層において溝13を挟んで形成された、n型のソース層7と、溝13と、ソース層7の一部とを覆って形成された、層間絶縁膜6と、ベース層10および層間絶縁膜6を覆って配置された、表面電極2と、表面電極2上に部分的に形成された絶縁層5と、絶縁層5の端部を覆い、かつ、表面電極2上の絶縁層5が形成されていない領域を覆って形成された接合層4Bと、接合層4B上に形成されたはんだ層3と、はんだ層3上に配置されたリードフレーム1とを備える。
Claims (5)
- 第1導電型のドリフト層と、
前記ドリフト層上のうちの部分領域である第1領域に形成された、ゲート構造と、
前記第1領域および前記ドリフト層上のうちの他の領域である第2領域を覆って配置された、表面電極と、
前記表面電極上に部分的に形成された接合層と、
前記接合層上に形成されたはんだ層と、
前記はんだ層上に配置されたリードフレームとを備え、
前記接合層は前記第1領域に対応する前記表面電極上の領域を覆い、かつ、前記接合層の端部の全体は前記第2領域に対応する前記表面電極上の領域に位置し、
前記第2領域において、ダイオードが形成されていることを特徴とする、
半導体装置。 - 前記ゲート構造が、
前記ドリフト層上の前記第1領域に形成された、第2導電型のベース層と、
前記ベース層表層から前記ドリフト層内に達して形成された溝と、
前記溝の側面および底面に沿って形成されたゲート絶縁膜と、
前記溝内の前記ゲート絶縁膜の内側に形成されたゲート電極と、
前記ベース層表層において前記溝を挟んで形成された、第1導電型のソース層と、
前記溝と、前記ソース層の一部とを覆って形成された、第1層間絶縁膜とを備えることを特徴とする、
請求項1に記載の半導体装置。 - 前記ベース層は、前記ドリフト層上の前記第2領域においても形成され、
前記第2領域において、前記ドリフト層と前記ベース層との間のPN接合を有するPiNダイオードが形成されていることを特徴とする、
請求項2に記載の半導体装置。 - 前記第2領域において、前記ドリフト層と前記表面電極との間のショットキー接合を有するショットキーバリアダイオードが形成されていることを特徴とする、
請求項1または2に記載の半導体装置。 - 第1導電型のドリフト層と、
前記ドリフト層上のうちの部分領域である第1領域に形成された、ゲート構造と、
前記第1領域および前記ドリフト層上のうちの他の領域である第2領域を覆って配置された、表面電極と、
前記表面電極上に部分的に形成された接合層と、
前記接合層上に形成されたはんだ層と、
前記はんだ層上に配置されたリードフレームと、
前記第2領域上に配置された配線構造とを備え、
前記接合層は前記第1領域に対応する前記表面電極上の領域を覆い、かつ、前記接合層の端部の全体は前記第2領域に対応する前記表面電極上の領域に位置し、
前記表面電極は、前記配線構造を覆って配置され、
前記配線構造は、
ポリシリコンと、
前記ポリシリコンを覆って形成された第2層間絶縁膜とを備えることを特徴とする、
半導体装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2013/075235 WO2015040712A1 (ja) | 2013-09-19 | 2013-09-19 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016222927A Division JP2017069569A (ja) | 2016-11-16 | 2016-11-16 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP6046262B2 true JP6046262B2 (ja) | 2016-12-14 |
JPWO2015040712A1 JPWO2015040712A1 (ja) | 2017-03-02 |
Family
ID=52688397
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015537502A Active JP6046262B2 (ja) | 2013-09-19 | 2013-09-19 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP6046262B2 (ja) |
CN (1) | CN105556661B (ja) |
DE (1) | DE112013007447B4 (ja) |
WO (1) | WO2015040712A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6264334B2 (ja) * | 2015-07-21 | 2018-01-24 | トヨタ自動車株式会社 | 半導体装置 |
JP6299789B2 (ja) | 2016-03-09 | 2018-03-28 | トヨタ自動車株式会社 | スイッチング素子 |
JP6460016B2 (ja) * | 2016-03-09 | 2019-01-30 | トヨタ自動車株式会社 | スイッチング素子 |
JP6588363B2 (ja) | 2016-03-09 | 2019-10-09 | トヨタ自動車株式会社 | スイッチング素子 |
DE102018101392A1 (de) * | 2017-01-24 | 2018-07-26 | Toyota Jidosha Kabushiki Kaisha | Halbleitereinrichtung und verfahren zum herstellen derselben |
US10944015B2 (en) | 2017-08-24 | 2021-03-09 | Flosfia Inc. | Semiconductor device |
JP7248962B2 (ja) | 2017-08-24 | 2023-03-30 | 株式会社Flosfia | 半導体装置 |
CN110383489B (zh) | 2017-09-05 | 2023-07-04 | 富士电机株式会社 | 碳化硅半导体装置及碳化硅半导体装置的制造方法 |
JP7013735B2 (ja) | 2017-09-05 | 2022-02-01 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
CN113039630A (zh) * | 2018-11-20 | 2021-06-25 | 三菱电机株式会社 | 半导体装置以及半导体装置的制造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010141170A (ja) * | 2008-12-12 | 2010-06-24 | Denso Corp | 半導体装置の製造方法 |
JP2013045973A (ja) * | 2011-08-25 | 2013-03-04 | Panasonic Corp | 半導体装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6803667B2 (en) | 2001-08-09 | 2004-10-12 | Denso Corporation | Semiconductor device having a protective film |
JP4078993B2 (ja) | 2003-01-27 | 2008-04-23 | 三菱電機株式会社 | 半導体装置 |
JP2007142138A (ja) | 2005-11-18 | 2007-06-07 | Mitsubishi Electric Corp | 半導体装置 |
JP2007266483A (ja) * | 2006-03-29 | 2007-10-11 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US8507352B2 (en) | 2008-12-10 | 2013-08-13 | Denso Corporation | Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode |
JP5279632B2 (ja) * | 2009-06-25 | 2013-09-04 | 三菱電機株式会社 | 半導体モジュール |
DE102010038933A1 (de) * | 2009-08-18 | 2011-02-24 | Denso Corporation, Kariya-City | Halbleitervorrichtung mit Halbleiterchip und Metallplatte und Verfahren zu deren Fertigung |
JP2011066371A (ja) * | 2009-08-18 | 2011-03-31 | Denso Corp | 半導体装置およびその製造方法 |
JP2013004943A (ja) * | 2011-06-22 | 2013-01-07 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
-
2013
- 2013-09-19 JP JP2015537502A patent/JP6046262B2/ja active Active
- 2013-09-19 DE DE112013007447.8T patent/DE112013007447B4/de active Active
- 2013-09-19 WO PCT/JP2013/075235 patent/WO2015040712A1/ja active Application Filing
- 2013-09-19 CN CN201380079685.7A patent/CN105556661B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010141170A (ja) * | 2008-12-12 | 2010-06-24 | Denso Corp | 半導体装置の製造方法 |
JP2013045973A (ja) * | 2011-08-25 | 2013-03-04 | Panasonic Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN105556661A (zh) | 2016-05-04 |
DE112013007447T5 (de) | 2016-06-16 |
CN105556661B (zh) | 2018-07-24 |
JPWO2015040712A1 (ja) | 2017-03-02 |
DE112013007447B4 (de) | 2022-01-27 |
WO2015040712A1 (ja) | 2015-03-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6046262B2 (ja) | 半導体装置 | |
US10643967B2 (en) | Power semiconductor device that includes a copper layer disposed on an electrode and located away from a polyimide layer and method for manufacturing the power semiconductor device | |
JP5232367B2 (ja) | 半導体装置 | |
US10115798B2 (en) | Semiconductor device and method of manufacturing the same | |
TW201539690A (zh) | 半導體裝置 | |
US9224698B1 (en) | Semiconductor device | |
JP6366723B2 (ja) | 半導体装置およびその製造方法 | |
JP2017069569A (ja) | 半導体装置 | |
JP2019016738A (ja) | 半導体装置 | |
KR101734712B1 (ko) | 파워모듈 | |
JP6192561B2 (ja) | 電力用半導体装置 | |
JP6834436B2 (ja) | 半導体装置 | |
JP7099115B2 (ja) | 半導体装置 | |
JP5777319B2 (ja) | 半導体装置 | |
JP2015144169A (ja) | 半導体モジュール | |
JP2013113638A (ja) | 半導体装置 | |
US9553067B2 (en) | Semiconductor device | |
JP6316221B2 (ja) | 半導体装置 | |
JP2017073406A (ja) | 電極リードおよび半導体装置 | |
JP4649948B2 (ja) | 半導体装置 | |
KR102394542B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
JP6379494B2 (ja) | パワーモジュール | |
JP7310590B2 (ja) | 半導体装置 | |
JP7274954B2 (ja) | 半導体装置 | |
JP6269417B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160912 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20161018 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20161116 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6046262 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |