JP6025823B2 - 負べベルにより終端された高阻止電圧を有するSiCデバイス - Google Patents
負べベルにより終端された高阻止電圧を有するSiCデバイス Download PDFInfo
- Publication number
- JP6025823B2 JP6025823B2 JP2014511405A JP2014511405A JP6025823B2 JP 6025823 B2 JP6025823 B2 JP 6025823B2 JP 2014511405 A JP2014511405 A JP 2014511405A JP 2014511405 A JP2014511405 A JP 2014511405A JP 6025823 B2 JP6025823 B2 JP 6025823B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- edge termination
- stages
- sic
- sic semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/40—Vertical BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D18/00—Thyristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/192—Base regions of thyristors
- H10D62/199—Anode base regions of thyristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/108,366 US9337268B2 (en) | 2011-05-16 | 2011-05-16 | SiC devices with high blocking voltage terminated by a negative bevel |
| US13/108,366 | 2011-05-16 | ||
| PCT/US2012/037215 WO2012158438A1 (en) | 2011-05-16 | 2012-05-10 | Sic devices with high blocking voltage terminated by a negative bevel |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016120345A Division JP6407920B2 (ja) | 2011-05-16 | 2016-06-17 | 負べベルにより終端された高阻止電圧を有するSiCデバイス |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014518016A JP2014518016A (ja) | 2014-07-24 |
| JP2014518016A5 JP2014518016A5 (enExample) | 2016-04-28 |
| JP6025823B2 true JP6025823B2 (ja) | 2016-11-16 |
Family
ID=46177520
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014511405A Active JP6025823B2 (ja) | 2011-05-16 | 2012-05-10 | 負べベルにより終端された高阻止電圧を有するSiCデバイス |
| JP2016120345A Active JP6407920B2 (ja) | 2011-05-16 | 2016-06-17 | 負べベルにより終端された高阻止電圧を有するSiCデバイス |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016120345A Active JP6407920B2 (ja) | 2011-05-16 | 2016-06-17 | 負べベルにより終端された高阻止電圧を有するSiCデバイス |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9337268B2 (enExample) |
| EP (1) | EP2710635B1 (enExample) |
| JP (2) | JP6025823B2 (enExample) |
| CN (1) | CN103748684B (enExample) |
| TW (1) | TWI515914B (enExample) |
| WO (1) | WO2012158438A1 (enExample) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9349797B2 (en) | 2011-05-16 | 2016-05-24 | Cree, Inc. | SiC devices with high blocking voltage terminated by a negative bevel |
| US9640617B2 (en) | 2011-09-11 | 2017-05-02 | Cree, Inc. | High performance power module |
| CN103918079B (zh) * | 2011-09-11 | 2017-10-31 | 科锐 | 包括具有改进布局的晶体管的高电流密度功率模块 |
| WO2013107508A1 (en) * | 2012-01-18 | 2013-07-25 | Fairchild Semiconductor Corporation | Bipolar junction transistor with spacer layer and method of manufacturing the same |
| JP6419414B2 (ja) * | 2013-03-22 | 2018-11-07 | 株式会社東芝 | SiCエピタキシャルウェハおよび半導体装置 |
| US9704718B2 (en) | 2013-03-22 | 2017-07-11 | Infineon Technologies Austria Ag | Method for manufacturing a silicon carbide device and a silicon carbide device |
| US9236458B2 (en) * | 2013-07-11 | 2016-01-12 | Infineon Technologies Ag | Bipolar transistor and a method for manufacturing a bipolar transistor |
| US9425265B2 (en) | 2013-08-16 | 2016-08-23 | Cree, Inc. | Edge termination technique for high voltage power devices having a negative feature for an improved edge termination structure |
| CN104882357A (zh) * | 2014-02-28 | 2015-09-02 | 株洲南车时代电气股份有限公司 | 半导体器件耐压终端结构及其应用于SiC器件的制造方法 |
| JP6871562B2 (ja) * | 2016-11-16 | 2021-05-12 | 富士電機株式会社 | 炭化珪素半導体素子およびその製造方法 |
| CN106684132B (zh) * | 2016-12-29 | 2019-10-01 | 西安电子科技大学 | 基于有源区沟槽结构的碳化硅双极型晶体管及其制作方法 |
| CN110521000A (zh) * | 2017-04-24 | 2019-11-29 | 力特半导体(无锡)有限公司 | 改进的场阻止晶闸管结构及其制造方法 |
| EP3496153B1 (en) | 2017-12-05 | 2021-05-19 | STMicroelectronics S.r.l. | Manufacturing method of a semiconductor device with efficient edge structure |
| CN107910360A (zh) * | 2017-12-06 | 2018-04-13 | 中国工程物理研究院电子工程研究所 | 一种新型碳化硅小角度倾斜台面终端结构及其制备方法 |
| CN109065614A (zh) * | 2018-08-22 | 2018-12-21 | 电子科技大学 | 一种碳化硅门极可关断晶闸管 |
| US12218255B2 (en) * | 2018-10-09 | 2025-02-04 | National Technology & Engineering Solutions Of Sandia, Llc | High voltage gallium nitride vertical PN diode |
| CN109346515B (zh) * | 2018-11-15 | 2021-06-08 | 电子科技大学 | 一种碳化硅绝缘栅双极型晶体管 |
| CN109346517B (zh) * | 2018-11-15 | 2021-06-08 | 电子科技大学 | 一种碳化硅mos栅控晶闸管 |
| US11579645B2 (en) * | 2019-06-21 | 2023-02-14 | Wolfspeed, Inc. | Device design for short-circuitry protection circuitry within transistors |
| CN110690268B (zh) * | 2019-09-19 | 2025-12-02 | 清华大学 | 具有p型漂移区的gct芯片结构及制备方法 |
| JP7074173B2 (ja) * | 2020-10-16 | 2022-05-24 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
| JP7628865B2 (ja) | 2021-03-31 | 2025-02-12 | 株式会社デンソー | ダイオードとその製造方法 |
| CN114783875B (zh) * | 2022-06-22 | 2022-12-13 | 泰科天润半导体科技(北京)有限公司 | 具有四层外延的碳化硅凹槽mos栅控晶闸管的制造方法 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3581348D1 (de) | 1984-09-28 | 1991-02-21 | Siemens Ag | Verfahren zum herstellen eines pn-uebergangs mit hoher durchbruchsspannung. |
| US4648174A (en) | 1985-02-05 | 1987-03-10 | General Electric Company | Method of making high breakdown voltage semiconductor device |
| JP2850694B2 (ja) | 1993-03-10 | 1999-01-27 | 株式会社日立製作所 | 高耐圧プレーナ型半導体装置 |
| US5970324A (en) | 1994-03-09 | 1999-10-19 | Driscoll; John Cuervo | Methods of making dual gated power electronic switching devices |
| US5449925A (en) * | 1994-05-04 | 1995-09-12 | North Carolina State University | Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices |
| US5967795A (en) * | 1995-08-30 | 1999-10-19 | Asea Brown Boveri Ab | SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
| SE9700156D0 (sv) | 1997-01-21 | 1997-01-21 | Abb Research Ltd | Junction termination for Si C Schottky diode |
| SE0004377D0 (sv) | 2000-11-29 | 2000-11-29 | Abb Research Ltd | A semiconductor device and a method for production thereof |
| JP4604241B2 (ja) | 2004-11-18 | 2011-01-05 | 独立行政法人産業技術総合研究所 | 炭化ケイ素mos電界効果トランジスタおよびその製造方法 |
| US7498651B2 (en) | 2004-11-24 | 2009-03-03 | Microsemi Corporation | Junction termination structures for wide-bandgap power devices |
| DE102005047102B3 (de) | 2005-09-30 | 2007-05-31 | Infineon Technologies Ag | Halbleiterbauelement mit pn-Übergang |
| US7345310B2 (en) * | 2005-12-22 | 2008-03-18 | Cree, Inc. | Silicon carbide bipolar junction transistors having a silicon carbide passivation layer on the base region thereof |
| US7372087B2 (en) | 2006-06-01 | 2008-05-13 | Northrop Grumman Corporation | Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage |
| JP5147244B2 (ja) * | 2007-01-17 | 2013-02-20 | 関西電力株式会社 | バイポーラ型半導体素子 |
| WO2009061340A1 (en) | 2007-11-09 | 2009-05-14 | Cree, Inc. | Power semiconductor devices with mesa structures and buffer layers including mesa steps |
| US8097919B2 (en) * | 2008-08-11 | 2012-01-17 | Cree, Inc. | Mesa termination structures for power semiconductor devices including mesa step buffers |
| US7759186B2 (en) | 2008-09-03 | 2010-07-20 | The United States Of America As Represented By The Secretary Of The Navy | Method for fabricating junction termination extension with formation of photosensitive dopant mask to control doping profile and lateral width for high-voltage electronic devices |
| SE537101C2 (sv) * | 2010-03-30 | 2015-01-07 | Fairchild Semiconductor | Halvledarkomponent och förfarande för utformning av en struktur i ett målsubstrat för tillverkning av en halvledarkomponent |
| JP6050563B2 (ja) | 2011-02-25 | 2016-12-21 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
-
2011
- 2011-05-16 US US13/108,366 patent/US9337268B2/en active Active
-
2012
- 2012-05-10 JP JP2014511405A patent/JP6025823B2/ja active Active
- 2012-05-10 WO PCT/US2012/037215 patent/WO2012158438A1/en not_active Ceased
- 2012-05-10 CN CN201280035253.1A patent/CN103748684B/zh active Active
- 2012-05-10 EP EP12724225.3A patent/EP2710635B1/en active Active
- 2012-05-16 TW TW101117452A patent/TWI515914B/zh active
-
2016
- 2016-06-17 JP JP2016120345A patent/JP6407920B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP6407920B2 (ja) | 2018-10-17 |
| EP2710635A1 (en) | 2014-03-26 |
| TWI515914B (zh) | 2016-01-01 |
| WO2012158438A4 (en) | 2013-01-03 |
| US20120292636A1 (en) | 2012-11-22 |
| JP2016189480A (ja) | 2016-11-04 |
| JP2014518016A (ja) | 2014-07-24 |
| CN103748684A (zh) | 2014-04-23 |
| US9337268B2 (en) | 2016-05-10 |
| TW201308620A (zh) | 2013-02-16 |
| CN103748684B (zh) | 2017-06-09 |
| WO2012158438A1 (en) | 2012-11-22 |
| EP2710635B1 (en) | 2018-01-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6407920B2 (ja) | 負べベルにより終端された高阻止電圧を有するSiCデバイス | |
| US11837629B2 (en) | Power semiconductor devices having gate trenches and buried edge terminations and related methods | |
| KR102216528B1 (ko) | 주입된 측벽들을 가진 게이트 트렌치들을 갖는 전력 반도체 디바이스들 및 관련 방법들 | |
| JP5372002B2 (ja) | メサ構造とメサ段差を含むバッファ層とを備えた電力半導体デバイス | |
| JP5185228B2 (ja) | 電力半導体デバイスのためのメサ終端構造とメサ終端構造をもつ電力半導体デバイスを形成するための方法 | |
| CN101689562B (zh) | 半导体器件 | |
| US7541660B2 (en) | Power semiconductor device | |
| US10109725B2 (en) | Reverse-conducting semiconductor device | |
| JP5196766B2 (ja) | 半導体装置 | |
| US9349797B2 (en) | SiC devices with high blocking voltage terminated by a negative bevel | |
| JP6833848B2 (ja) | 面積効率の良いフローティングフィールドリング終端 | |
| JP5473397B2 (ja) | 半導体装置およびその製造方法 | |
| JP6335795B2 (ja) | 負ベベルにより終端した、高い阻止電圧を有するSiC素子 | |
| WO2018154963A1 (ja) | 半導体装置 | |
| JP6362702B2 (ja) | バイポーラノンパンチスルーパワー半導体デバイス | |
| CN104465733A (zh) | 功率半导体器件 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20141106 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160307 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160318 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160617 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160913 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20161011 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6025823 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |