JP6022469B2 - 基板のダブルパターニング方法 - Google Patents
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- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
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- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
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- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
- G03F7/405—Treatment with inorganic or organometallic reagents after imagewise removal
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T428/00—Stock material or miscellaneous articles
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Description
Claims (18)
- 基板のダブルパターニング方法であって:
放射線感受性材料の第1層を生成する工程;
第1リソグラフィ処理を用いることによって、前記放射線感受性材料の第1層中に第1限界寸法(CD)により特徴付けられる第1パターンを準備する工程;
前記第1パターンを準備する工程に続き、第1CDスリミング処理を実行して前記第1CDを第1減少CDへ減少させる工程であって、前記第1CDスリミング処理は:
前記第1パターンの表面上に酸を含む第1処理化合物を塗布する工程;
前記酸を前記表面から前記第1パターンの表面領域へ拡散させることによって、前記第1パターンの表面領域の溶解度を第1所定の深さまで変化させることで、前記の変化した表面領域が第1現像溶液中で可溶となるように前記基板をベーキングする工程;及び、
前記第1現像溶液を前記基板上に供給することによって、前記第1現像溶液を前記の変化した表面領域へ塗布することで、前記第1パターンの前記表面領域を前記第1所定の深さまで除去する工程、を含む、工程;
フリージング処理を用いることによって、前記放射線感受性材料の第1層中の前記第1減少CDを有する第1パターンをフリージングする工程;
前記放射線感受性材料の第1層中の前記第1減少CDを有する第1パターン上に放射線感受性材料の第2層を生成する工程;
第2リソグラフィ処理を用いることによって、前記放射線感受性材料の第2層中に第2CDにより特徴付けられる第2パターンを準備する工程;並びに、
前記第2パターンを準備する工程に続き、第2CDスリミング処理を実行して前記第2CDを第2減少CDへ減少させる工程であって、前記第2CDスリミング処理は:
前記第2パターンの表面上に酸を含む第2処理化合物を塗布する工程;
前記酸を前記表面から前記第2パターンの表面領域へ拡散させることによって、前記第2パターンの表面領域の溶解度を第2所定の深さまで変化させることで、前記の変化した表面領域が第2現像溶液中で可溶となるように前記基板をベーキングする工程;及び、
前記第2現像溶液を前記基板上に供給することによって、前記第2現像溶液を前記の変化した表面領域へ塗布することで、前記第2パターンの前記表面領域を前記第2所定の深さまで除去する工程、を含む、工程;
を有する方法。 - 前記放射線感受性材料の第1層が熱的に硬化可能なフリージングレジストを有し、かつ、
前記フリージング処理を用いて前記放射線感受性材料の第1層中の第1パターンをフリージングする工程は、前記放射線感受性材料の第1層をベーキングすることで、前記第1減少CDを有する第1パターンを熱的に硬化して保持する工程を有する、
請求項1に記載の方法。 - 前記放射線感受性材料の第1層が電磁(EM)放射線により硬化可能なフリージング材料を有し、かつ、
前記フリージング処理を用いて前記放射線感受性材料の第1層中の第1パターンをフリージングする工程は、前記放射線感受性材料の第1層をEM放射線に曝露することで、前記第1減少CDを有する第1パターンを放射線により硬化して保持する工程を有する、
請求項1に記載の方法。 - 前記放射線感受性材料の第1層が化学的に硬化可能なフリージング材料を有し、かつ、
前記フリージング処理を用いて前記放射線感受性材料の第1層中の第1パターンをフリージングする工程は、前記放射線感受性材料の第1層に化学物質を付与して反応させることで、前記第1減少CDを有する第1パターンを化学的に硬化して保持する工程を有する、
請求項1に記載の方法。 - 前記第1パターンと前記第2パターンを下地層へ転写する工程をさらに有する、請求項1に記載の方法。
- 1:1乃至1:2の範囲に属する前記第1パターンと前記第2パターンのラインパターンピッチを生成する工程をさらに有する請求項1に記載の方法であって、
前記第1パターンは第1ラインパターンを有し、かつ、前記第2パターンは第2ラインパターンを有する、
方法。 - 前記第1減少CDが30nm未満で、かつ、前記第2減少CDが30nm未満である、請求項1に記載の方法。
- 前記第1減少CDが25nm未満で、かつ、前記第2減少CDが25nm未満である、請求項1に記載の方法。
- 前記第1CDスリミング処理が:
前記第1処理化合物を塗布する工程の前に、30℃を超える熱い現像温度にまで加熱された第1の加熱された現像溶液を前記基板上に供給する工程;
を有する、請求項1に記載の方法。 - 前記第2CDスリミング処理が:
前記第2処理化合物を塗布する工程の前に、30℃を超える熱い現像温度にまで加熱された第2の加熱された現像溶液を前記基板上に供給する工程;
を有する、請求項1に記載の方法。 - 前記第1パターンと前記第2パターンの破壊を防止するように、前記第1CDスリミング処理、前記第2CDスリミング処理、前記フリージング処理、前記第1リソグラフィ処理、及び/又は前記第2リソグラフィ処理についての少なくとも1つの処理パラメータを最適化する工程をさらに有する、請求項1に記載の方法。
- 前記フリージング処理が行われた第1パターン内の第1減少CDへの影響を最小にしながら第2パターン内に第2減少CDを生成するように、前記第1CDスリミング処理、前記第2CDスリミング処理、前記フリージング処理、前記第1リソグラフィ処理、及び/又は前記第2リソグラフィ処理についての少なくとも1つの処理パラメータを最適化する工程をさらに有する、請求項2に記載の方法。
- 前記第2パターン内の第2CDよりも大きな前記第1パターン内の第1CDを準備する工程をさらに有する、請求項1に記載の方法。
- 前記第1CDが、前記第2CDよりも最大25%大きい、請求項13に記載の方法。
- 前記第1CDが、前記第2CDよりも最大10%大きい、請求項13に記載の方法。
- 前記放射線感受性材料の第1層を生成する工程が、フォトレジストによって前記基板をスピンコーティングする工程を有し、かつ、
前記放射線感受性材料の第2層を生成する工程が、フォトレジストによって前記基板をスピンコーティングする工程を有する、
請求項1に記載の方法。 - 前記放射線感受性材料の第1層中に第1パターンを準備する工程が:
放射線曝露システム内の第1位置合わせ位置にて前記基板を位置合わせする工程;
前記放射線感受性材料の第1層を第1放射線に曝露する工程;
前記放射線感受性材料の第1層の第1曝露後ベーキングを実行する工程;
前記第1曝露後ベーキング後に前記基板を冷却する工程;及び、
前記放射線感受性材料の第1層を現像して該第1層内に前記第1パターンを生成する工程;
を有する、請求項1に記載の方法。 - 前記放射線感受性材料の第2層中に第2パターンを準備する工程が:
放射線曝露システム内の第2位置合わせ位置にて前記基板を位置合わせする工程;
前記放射線感受性材料の第2層を第2放射線に曝露する工程;
前記放射線感受性材料の第2層の第2曝露後ベーキングを実行する工程;
前記第2曝露後ベーキング後に前記基板を冷却する工程;及び、
前記放射線感受性材料の第2層を現像して該第2層内に前記第2パターンを生成する工程;
を有する、請求項1に記載の方法。
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US41649610P | 2010-11-23 | 2010-11-23 | |
US61/416,496 | 2010-11-23 | ||
US13/158,868 US8940475B2 (en) | 2010-11-23 | 2011-06-13 | Double patterning with inline critical dimension slimming |
US13/158,868 | 2011-06-13 | ||
PCT/US2011/060386 WO2012071193A2 (en) | 2010-11-23 | 2011-11-11 | Double patterning with inline critical dimension slimming |
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US8980651B2 (en) * | 2011-09-30 | 2015-03-17 | Tokyo Electron Limited | Overlay measurement for a double patterning |
US8980111B2 (en) | 2012-05-15 | 2015-03-17 | Tokyo Electron Limited | Sidewall image transfer method for low aspect ratio patterns |
US9177820B2 (en) | 2012-10-24 | 2015-11-03 | Globalfoundries U.S. 2 Llc | Sub-lithographic semiconductor structures with non-constant pitch |
KR102223035B1 (ko) | 2014-03-05 | 2021-03-04 | 삼성전자주식회사 | 반도체 소자의 패턴 형성 방법 |
US9508713B2 (en) | 2014-03-05 | 2016-11-29 | International Business Machines Corporation | Densely spaced fins for semiconductor fin field effect transistors |
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US9691587B2 (en) * | 2014-06-30 | 2017-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dimension measurement apparatus calibration standard and method for forming the same |
US9472506B2 (en) | 2015-02-25 | 2016-10-18 | International Business Machines Corporation | Registration mark formation during sidewall image transfer process |
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US9991132B2 (en) * | 2015-04-17 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithographic technique incorporating varied pattern materials |
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