JP5983953B2 - ピッチを2倍にするリソグラフィ方法 - Google Patents
ピッチを2倍にするリソグラフィ方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 37
- 239000010410 layer Substances 0.000 claims description 164
- 125000006850 spacer group Chemical group 0.000 claims description 106
- 239000004020 conductor Substances 0.000 claims description 54
- 238000005530 etching Methods 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 52
- 230000000295 complement effect Effects 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 21
- 239000011810 insulating material Substances 0.000 claims description 18
- 238000010894 electron beam technology Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910052500 inorganic mineral Inorganic materials 0.000 claims description 10
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- 238000001459 lithography Methods 0.000 description 27
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000000151 deposition Methods 0.000 description 10
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
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- 229910052710 silicon Inorganic materials 0.000 description 3
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
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- 150000001879 copper Chemical class 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- B44C1/00—Processes, not specifically provided for elsewhere, for producing decorative surface effects
- B44C1/22—Removing surface-material, e.g. by engraving, by etching
- B44C1/227—Removing surface-material, e.g. by engraving, by etching by etching
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
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Description
−基板上に犠牲層を形成し、
−第1の細片に沿って犠牲層のエッチングを行ない、
−そのようにエッチングされた犠牲層の縁の全てに沿ってスペーサを形成し、
−求める高密度ラインを形成すべくスペーサだけを残すように犠牲層を除去することである。
−スペーサの材料とは異なる材料の非感光性層であって、スペーサの高さに等しい制限以下の厚さを有する、換言すればスペーサから溢れ出ることがない非感光層に重ね合わされた、光子またはイオンまたは電子照射に感光する層の組み合わせを用いて、
−または、厚さがスペーサの高さ以下であってスペーサ間に堆積され、そのような種類の照射に感光する単一の層に基づいて、形成することができる。
Claims (13)
- いくつかの低密度の部分パターンの組み合わせに基づいて高密度のパターンをエッチングするリソグラフィ方法であって、
基板(10)上への犠牲層(12)の形成および平行なラインを含む第1の部分パターンに従い前記犠牲層のエッチングを行ない、次いでこのようにエッチングされた前記犠牲層の要素の縁上にスペーサ(16)を形成し、次いで前記スペーサだけを残して前記犠牲層を除去して、前記スペーサが2本の隣接する中心ラインおよび2本の外側ラインを含む少なくとも4本の平行なラインの第2の部分パターンを画定し、
前記スペーサ間において前記スペーサの高さ未満の厚さの前記スペーサとは異なる材料の補完層(22)の堆積を含み、
前記補完層を第3の部分パターンに従い局所的にエッチングすることにより前記第2および第3の部分パターンの組み合わせから得られる最終パターンを前記基板上に画定し、
前記第3の部分パターンが、前記2本の隣接する中心ライン間において前記スペーサの前記2本の隣接する中心ラインに垂直な方向に延在し、且つ前記方向において前記2本の隣接する中心ラインを越えることなく前記2本の隣接する中心ラインで終端する少なくとも1個の領域を含む
ことを特徴とする方法。 - 前記スペーサとは異なる材料の前記補完層が光子または電子またはイオン照射に感光する材料の層であり、前記エッチングがそのような種類の照射への露光により実行されることを特徴とする、請求項1に記載の方法。
- 前記局所的エッチングの後で、前記感光層の断面が前記スペーサに沿って流動可能にする熱処理の追加的ステップを含むことを特徴とする、請求項2に記載の方法。
- 前記感光性材料の層が光子照射に感光し、前記層の材料が前記スペーサを形成する材料とほぼ同じ屈折率を有することを特徴とする、請求項2に記載の方法。
- 前記基板が表面層(12、110)を含み、前記層の下側の前記基板をエッチングするための鉱物マスクを形成すること、およびスペーサと補完層が存在しない領域の最終パターンを用いて前記基板のエッチングの前に鉱物マスクをエッチングすることを特徴とする、請求項1〜4のいずれか1項に記載の方法。
- 前記基板(10)が、前記鉱物マスクを介してエッチング除去されることを特徴とする、請求項5に記載のリソグラフィ方法。
- 前記基板内にエッチングされた前記領域が、前記エッチング除去された領域から溢れ出すことなく、前記基板の表面と同一表面の材料(25)で埋められることを特徴とする、請求項6に記載の方法。
- 前記基板が絶縁材料で作成されていて、前記基板内にエッチングされた前記領域が導体の密なネットワークを形成すべく導電材料で埋めることを特徴とする、請求項7に記載の方法。
- 前記鉱物マスクのエッチングの後で、新たな層(120)が前記スペーサの高さ未満の厚さに堆積され、前記層が局所的にエッチング除去されて、前記基板が絶縁材料で作成されていて、前記基板の前記絶縁材料が、前記新たな層(120)または前記スペーサ(116)のいずれにも覆われていないスペースにおいて第1の深さ(P1)までエッチングされることを特徴とする、請求項5に記載の方法。
- 前記第1の深さまでのエッチングの後で、前記新たな層(120)が除去されて、前記基板の前記絶縁材料が第2の深さ(P2)までエッチングされることを特徴とする、請求項9に記載の方法。
- 前記基板が、前記第1および第2の深さの合計に等しい深さに埋め込まれた導体(102)の第1のネットワークを含み、前記2段の深さの合計にわたり前記基板の前記絶縁材料内にエッチングされた箇所が前記埋め込まれた導体へのアクセスビア孔(124)を形成し、前記基板の前記絶縁材料内にエッチングされた箇所が導体金属(130)で埋められ、前記箇所のうち、前記第2の深さ(P2)までしかエッチングされていないものが、前記ビア孔を介して前記第1のネットワークに接続された導体の第2のネットワークを形成することを特徴とする、請求項10に記載の方法。
- 前記基板が絶縁材料で作成されていて、前記鉱物マスク(110)のエッチングの後で、前記基板の絶縁材料(108)が、前記マスクにより保護されていない箇所で第1の深さまでエッチング除去され、次いで電子ビームに感光する新たな層が前記スペーサの高さ以下の厚さに堆積されて、前記感光層が電子ビームによりエッチングされ、前記基板の前記絶縁材料が、前記感光層で覆われていないスペースにおいて第2の深さまでエッチングされて、前記感光層および前記スペーサが除去され、最後に、前記絶縁材料内にエッチングされた箇所が導電金属で埋められることを特徴とする、請求項5に記載の方法。
- 前記基板が、前記第1および第2の深さの合計に等しい深さに埋め込まれた導体の第1のネットワークを含み、前記基板の前記絶縁材料内にエッチングされた箇所が導体金属で埋められ、前記箇所のうち、前記第1の深さまでしかエッチングされていないものが導体の第2のネットワークを形成し、前記第1および第2の深さの合計までエッチングされたものが前記第1のネットワークと前記第2のネットワークとの間を接続するビア孔を形成することを特徴とする、請求項12に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1002306A FR2960657B1 (fr) | 2010-06-01 | 2010-06-01 | Procede de lithographie a dedoublement de pas |
FR10/02306 | 2010-06-01 | ||
PCT/EP2011/058598 WO2011151243A1 (fr) | 2010-06-01 | 2011-05-25 | Procede de lithographie a dedoublement de pas |
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JP2013533611A JP2013533611A (ja) | 2013-08-22 |
JP5983953B2 true JP5983953B2 (ja) | 2016-09-06 |
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JP2013512838A Expired - Fee Related JP5983953B2 (ja) | 2010-06-01 | 2011-05-25 | ピッチを2倍にするリソグラフィ方法 |
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US (1) | US9156306B2 (ja) |
EP (1) | EP2577395B1 (ja) |
JP (1) | JP5983953B2 (ja) |
KR (1) | KR101997927B1 (ja) |
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WO (1) | WO2011151243A1 (ja) |
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FR3001306A1 (fr) | 2013-01-18 | 2014-07-25 | Commissariat Energie Atomique | Procede de fabrication d'un reseau de conducteurs sur un substrat au moyen de copolymeres a blocs |
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US9136168B2 (en) | 2013-06-28 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive line patterning |
US9614053B2 (en) | 2013-12-05 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacers with rectangular profile and methods of forming the same |
US9293343B2 (en) | 2014-07-02 | 2016-03-22 | Samsung Electronics Co., Ltd. | Method of forming patterns of semiconductor device |
US9406511B2 (en) * | 2014-07-10 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned double patterning |
US10678137B2 (en) * | 2014-09-22 | 2020-06-09 | Intel Corporation | Multi-pass patterning using nonreflecting radiation lithography on an underlying grating |
JP6481994B2 (ja) * | 2014-10-23 | 2019-03-13 | 東京エレクトロン株式会社 | 画素電極のパターン形成方法および形成システム |
JP6249970B2 (ja) * | 2015-01-30 | 2017-12-20 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
US9754791B2 (en) * | 2015-02-07 | 2017-09-05 | Applied Materials, Inc. | Selective deposition utilizing masks and directional plasma treatment |
TWI704647B (zh) * | 2015-10-22 | 2020-09-11 | 聯華電子股份有限公司 | 積體電路及其製程 |
WO2017111822A1 (en) * | 2015-12-24 | 2017-06-29 | Intel Corporation | Pitch division using directed self-assembly |
US10559492B2 (en) | 2017-11-15 | 2020-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Patterning methods for semiconductor devices and structures resulting therefrom |
KR102387947B1 (ko) | 2017-11-21 | 2022-04-18 | 삼성전자주식회사 | 오버레이 패턴을 갖는 반도체 소자 |
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US6667237B1 (en) * | 2000-10-12 | 2003-12-23 | Vram Technologies, Llc | Method and apparatus for patterning fine dimensions |
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JP2005129761A (ja) * | 2003-10-24 | 2005-05-19 | Toshiba Corp | ホールパターン形成方法及び半導体装置の製造方法 |
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US7960096B2 (en) * | 2008-02-11 | 2011-06-14 | International Business Machines Corporation | Sublithographic patterning method incorporating a self-aligned single mask process |
JP2010080942A (ja) * | 2008-08-25 | 2010-04-08 | Elpida Memory Inc | 半導体装置の製造方法 |
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WO2011151243A1 (fr) | 2011-12-08 |
FR2960657A1 (fr) | 2011-12-02 |
US20130087527A1 (en) | 2013-04-11 |
KR20130106290A (ko) | 2013-09-27 |
US9156306B2 (en) | 2015-10-13 |
KR101997927B1 (ko) | 2019-07-08 |
JP2013533611A (ja) | 2013-08-22 |
EP2577395B1 (fr) | 2019-08-28 |
EP2577395A1 (fr) | 2013-04-10 |
FR2960657B1 (fr) | 2013-02-22 |
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