JP5894206B2 - パッケージキャリア - Google Patents
パッケージキャリア Download PDFInfo
- Publication number
- JP5894206B2 JP5894206B2 JP2014067619A JP2014067619A JP5894206B2 JP 5894206 B2 JP5894206 B2 JP 5894206B2 JP 2014067619 A JP2014067619 A JP 2014067619A JP 2014067619 A JP2014067619 A JP 2014067619A JP 5894206 B2 JP5894206 B2 JP 5894206B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- patterned
- solder mask
- package carrier
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910000679 solder Inorganic materials 0.000 claims description 47
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000011889 copper foil Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 157
- 239000011162 core material Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 239000000969 carrier Substances 0.000 description 3
- 239000002335 surface treatment layer Substances 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000002775 capsule Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Description
110 着脱可能な支持板
112 誘電体層
114 銅箔層
116 剥離層
120a、120a’、120b、120c 回路基板
121a 上表面
121b、121c 第1表面
122a、122a’ 回路層
122b、122c 第1パターン化回路層
123a 下表面
123b、123c 第2表面
124b、124c 第2パターン化回路層
125a、125b、125c 第1はんだマスク層
126b、126c 絶縁層
127a、127b、127c 第2はんだマスク層
127a’ はんだマスク層
128b、128c 導電性スルーホール
130 表面処理層
200 パッケージ構造
210 チップ
220 ワイヤ
230 カプセル型接着剤
240 はんだ
T、T’、T’’、T’’’、T1、T2 厚さ
S1 頂表面
S2 底表面
Claims (9)
- 誘電体層と、銅箔層と、剥離層とを含み、前記誘電体層が、前記銅箔層と前記剥離層の間に配置された着脱可能な支持板と、
前記着脱可能な支持板に配置されて、前記剥離層に直接接触し、厚さが、30μm〜100μmの間である回路基板と
を含み、
前記回路基板が、
互いに向かい合う上表面と下表面を有する回路層と、
前記回路層の前記上表面に配置され、前記上表面の一部を露出する第1パターン化はんだマスク層と、
前記回路層の前記下表面に配置され、前記下表面の一部を露出する第2パターン化はんだマスク層と
を含み、前記剥離層および前記第2パターン化はんだマスク層が、コンフォーマルに配置され、前記第2パターン化はんだマスク層によって露出した前記下表面が、前記剥離層に直接接触し、前記第2パターン化はんだマスク層の側表面に前記剥離層を設けるパッケージキャリア。 - 前記回路層が、
第1パターン化回路層と、
第2パターン化回路層と、
前記第1パターン化回路層と前記第2パターン化回路層の間に配置され、互いに向かい合う第1表面と第2表面を有する絶縁層と、
前記絶縁層の前記第1表面および前記第2表面を通過して、前記第1パターン化回路層および前記第2パターン化回路層に電気接続された少なくとも1つの導電性スルーホールと、
を含み、前記第1パターン化はんだマスク層は、前記絶縁層の前記第1表面に配置され、前記第1パターン化回路層の一部を覆い、
前記第2パターン化はんだマスク層は、前記絶縁層の前記第2表面に配置され、前記第2パターン化回路層の一部を覆い、
前記剥離層および前記第2パターン化はんだマスク層が、コンフォーマルに配置され、前記第2パターン化はんだマスク層によって露出した前記第2パターン化回路層が、前記剥離層に直接接触する請求項1に記載のパッケージキャリア。 - 前記着脱可能な支持板の前記誘電体層の厚さが、前記絶縁層の厚さよりも大きい請求項2に記載のパッケージキャリア。
- 前記絶縁層の前記厚さが、30μmよりも小さいか、それに等しい請求項3に記載のパッケージキャリア。
- 前記第1パターン化回路層が、前記絶縁層の中に埋め込まれ、前記第1パターン化回路層の頂表面が、前記第1表面と一列に並んだ請求項2に記載のパッケージキャリア。
- 前記第1パターン化回路層が、前記絶縁層の前記第1表面に配置された請求項2に記載のパッケージキャリア。
- 前記第2パターン化回路層が、前記絶縁層の中に埋め込まれ、前記第2パターン化回路層の底表面が、前記第2表面と一列に並んだ請求項2に記載のパッケージキャリア。
- 前記第2パターン化回路層が、前記絶縁層の前記第2表面に配置された請求項2に記載のパッケージキャリア。
- 前記剥離層の材料が、金属材料または樹脂材料を含む請求項1に記載のパッケージキャリア。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW102135527A TWI527173B (zh) | 2013-10-01 | 2013-10-01 | 封裝載板 |
TW102135527 | 2013-10-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015073068A JP2015073068A (ja) | 2015-04-16 |
JP5894206B2 true JP5894206B2 (ja) | 2016-03-23 |
Family
ID=52739958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014067619A Active JP5894206B2 (ja) | 2013-10-01 | 2014-03-28 | パッケージキャリア |
Country Status (4)
Country | Link |
---|---|
US (1) | US9433099B2 (ja) |
JP (1) | JP5894206B2 (ja) |
CN (1) | CN104517929B (ja) |
TW (1) | TWI527173B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI587412B (zh) * | 2014-05-08 | 2017-06-11 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
TWI586236B (zh) * | 2015-01-13 | 2017-06-01 | 旭德科技股份有限公司 | 封裝載板及其製作方法 |
TWI542271B (zh) * | 2015-02-11 | 2016-07-11 | 旭德科技股份有限公司 | 封裝基板及其製作方法 |
CN113664084B (zh) * | 2020-05-14 | 2023-09-29 | 何崇文 | 卷式硬板的制作方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5971804A (en) * | 1997-06-30 | 1999-10-26 | Emc Corporation | Backplane having strip transmission line ethernet bus |
AU2001244016A1 (en) | 2000-03-31 | 2001-10-15 | Dyconex Patente Ag | Method for fabricating electrical connecting elements, and connecting element |
EP1432293A4 (en) * | 2001-09-28 | 2005-12-07 | Ibiden Co Ltd | PCB AND MANUFACTURING PROCESS FOR THE PCB |
US20030066679A1 (en) * | 2001-10-09 | 2003-04-10 | Castro Abram M. | Electrical circuit and method of formation |
JP4527991B2 (ja) | 2004-01-28 | 2010-08-18 | 株式会社日立製作所 | マルチチップモジュールの製造方法 |
CN1873935B (zh) * | 2005-05-31 | 2010-06-16 | 新光电气工业株式会社 | 配线基板的制造方法及半导体器件的制造方法 |
JP4146864B2 (ja) | 2005-05-31 | 2008-09-10 | 新光電気工業株式会社 | 配線基板及びその製造方法、並びに半導体装置及び半導体装置の製造方法 |
JP4800253B2 (ja) | 2007-04-04 | 2011-10-26 | 新光電気工業株式会社 | 配線基板の製造方法 |
JP5473838B2 (ja) | 2010-03-30 | 2014-04-16 | 日本電解株式会社 | 支持体金属箔付き複合金属層、これを用いた配線板とその製造方法、この配線板を用いた半導体パッケージの製造方法 |
JP2013165087A (ja) | 2010-05-31 | 2013-08-22 | Sanyo Electric Co Ltd | 半導体モジュールおよび半導体モジュールの製造方法 |
US8884431B2 (en) | 2011-09-09 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures for semiconductor devices |
JP5753471B2 (ja) * | 2011-10-12 | 2015-07-22 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
-
2013
- 2013-10-01 TW TW102135527A patent/TWI527173B/zh active
- 2013-11-06 US US14/072,803 patent/US9433099B2/en active Active
- 2013-11-12 CN CN201310560590.9A patent/CN104517929B/zh active Active
-
2014
- 2014-03-28 JP JP2014067619A patent/JP5894206B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2015073068A (ja) | 2015-04-16 |
TW201515170A (zh) | 2015-04-16 |
CN104517929B (zh) | 2017-10-13 |
CN104517929A (zh) | 2015-04-15 |
TWI527173B (zh) | 2016-03-21 |
US9433099B2 (en) | 2016-08-30 |
US20150092358A1 (en) | 2015-04-02 |
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