JP5881565B2 - 基板処理方法、プログラム及びコンピュータ記憶媒体 - Google Patents

基板処理方法、プログラム及びコンピュータ記憶媒体 Download PDF

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Publication number
JP5881565B2
JP5881565B2 JP2012196737A JP2012196737A JP5881565B2 JP 5881565 B2 JP5881565 B2 JP 5881565B2 JP 2012196737 A JP2012196737 A JP 2012196737A JP 2012196737 A JP2012196737 A JP 2012196737A JP 5881565 B2 JP5881565 B2 JP 5881565B2
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Japan
Prior art keywords
polymer
neutral layer
wafer
resist pattern
substrate processing
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Application number
JP2012196737A
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English (en)
Japanese (ja)
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JP2014053439A5 (https=
JP2014053439A (ja
Inventor
村松　誠
誠 村松
北野　高広
高広 北野
忠利 冨田
忠利 冨田
啓士 田内
啓士 田内
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP2012196737A priority Critical patent/JP5881565B2/ja
Priority to PCT/JP2013/072704 priority patent/WO2014038420A1/ja
Priority to TW102131552A priority patent/TW201426845A/zh
Publication of JP2014053439A publication Critical patent/JP2014053439A/ja
Publication of JP2014053439A5 publication Critical patent/JP2014053439A5/ja
Application granted granted Critical
Publication of JP5881565B2 publication Critical patent/JP5881565B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0452—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers
    • H10P72/0458—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers vertical arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0147—Film patterning
    • B81C2201/0149—Forming nanoscale microstructures using auto-arranging or self-assembling material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Analytical Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Formation Of Insulating Films (AREA)
JP2012196737A 2012-09-07 2012-09-07 基板処理方法、プログラム及びコンピュータ記憶媒体 Active JP5881565B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2012196737A JP5881565B2 (ja) 2012-09-07 2012-09-07 基板処理方法、プログラム及びコンピュータ記憶媒体
PCT/JP2013/072704 WO2014038420A1 (ja) 2012-09-07 2013-08-26 基板処理方法、コンピュータ記憶媒体及び基板処理システム
TW102131552A TW201426845A (zh) 2012-09-07 2013-09-02 基板處理方法、程式、電腦記憶媒體及基板處理系統

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012196737A JP5881565B2 (ja) 2012-09-07 2012-09-07 基板処理方法、プログラム及びコンピュータ記憶媒体

Publications (3)

Publication Number Publication Date
JP2014053439A JP2014053439A (ja) 2014-03-20
JP2014053439A5 JP2014053439A5 (https=) 2014-11-13
JP5881565B2 true JP5881565B2 (ja) 2016-03-09

Family

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Family Applications (1)

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JP2012196737A Active JP5881565B2 (ja) 2012-09-07 2012-09-07 基板処理方法、プログラム及びコンピュータ記憶媒体

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Country Link
JP (1) JP5881565B2 (https=)
TW (1) TW201426845A (https=)
WO (1) WO2014038420A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6177723B2 (ja) * 2014-04-25 2017-08-09 東京エレクトロン株式会社 基板処理方法、プログラム、コンピュータ記憶媒体及び基板処理システム
JP6267143B2 (ja) * 2015-03-05 2018-01-24 東京エレクトロン株式会社 基板処理方法、プログラム、コンピュータ記憶媒体及び基板処理システム
JP6346115B2 (ja) * 2015-03-24 2018-06-20 東芝メモリ株式会社 パターン形成方法
JP6494446B2 (ja) * 2015-06-23 2019-04-03 東京エレクトロン株式会社 基板処理方法、プログラム及びコンピュータ記憶媒体

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04364021A (ja) * 1991-06-11 1992-12-16 Sumitomo Electric Ind Ltd 半導体装置の製造方法
JP4753672B2 (ja) * 2005-09-16 2011-08-24 独立行政法人農業・食品産業技術総合研究機構 樹脂製マイクロチャネルアレイの製造方法及びこれを用いた血液測定方法
US7989026B2 (en) * 2008-01-12 2011-08-02 International Business Machines Corporation Method of use of epoxy-containing cycloaliphatic acrylic polymers as orientation control layers for block copolymer thin films
US7521094B1 (en) * 2008-01-14 2009-04-21 International Business Machines Corporation Method of forming polymer features by directed self-assembly of block copolymers
US8822139B2 (en) * 2010-04-14 2014-09-02 Asml Netherlands B.V. Method for providing an ordered layer of self-assemblable polymer for use in lithography
JP2013534542A (ja) * 2010-06-04 2013-09-05 エーエスエムエル ネザーランズ ビー．ブイ． 自己組織化可能な重合体及びリソグラフィにおける使用方法

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Publication number Publication date
TW201426845A (zh) 2014-07-01
WO2014038420A1 (ja) 2014-03-13
JP2014053439A (ja) 2014-03-20

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