JP5878362B2 - 半導体装置、半導体パッケージ及び半導体装置の製造方法 - Google Patents

半導体装置、半導体パッケージ及び半導体装置の製造方法 Download PDF

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Publication number
JP5878362B2
JP5878362B2 JP2011282076A JP2011282076A JP5878362B2 JP 5878362 B2 JP5878362 B2 JP 5878362B2 JP 2011282076 A JP2011282076 A JP 2011282076A JP 2011282076 A JP2011282076 A JP 2011282076A JP 5878362 B2 JP5878362 B2 JP 5878362B2
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Prior art keywords
layer
insulating layer
connection terminal
insulating
substrate
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JP2011282076A
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Japanese (ja)
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JP2013131720A5 (enExample
JP2013131720A (ja
Inventor
翔太 三木
翔太 三木
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2011282076A priority Critical patent/JP5878362B2/ja
Priority to US13/716,719 priority patent/US8987902B2/en
Publication of JP2013131720A publication Critical patent/JP2013131720A/ja
Publication of JP2013131720A5 publication Critical patent/JP2013131720A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2011282076A 2011-12-22 2011-12-22 半導体装置、半導体パッケージ及び半導体装置の製造方法 Active JP5878362B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011282076A JP5878362B2 (ja) 2011-12-22 2011-12-22 半導体装置、半導体パッケージ及び半導体装置の製造方法
US13/716,719 US8987902B2 (en) 2011-12-22 2012-12-17 Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011282076A JP5878362B2 (ja) 2011-12-22 2011-12-22 半導体装置、半導体パッケージ及び半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2013131720A JP2013131720A (ja) 2013-07-04
JP2013131720A5 JP2013131720A5 (enExample) 2014-10-02
JP5878362B2 true JP5878362B2 (ja) 2016-03-08

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Country Status (2)

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US (1) US8987902B2 (enExample)
JP (1) JP5878362B2 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123780B2 (en) * 2012-12-19 2015-09-01 Invensas Corporation Method and structures for heat dissipating interposers
US9299663B2 (en) 2014-05-19 2016-03-29 Micron Technology, Inc. Semiconductor devices and methods for backside photo alignment
JP2016018879A (ja) * 2014-07-08 2016-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
TWI566305B (zh) * 2014-10-29 2017-01-11 巨擘科技股份有限公司 製造三維積體電路的方法
TWI554174B (zh) * 2014-11-04 2016-10-11 上海兆芯集成電路有限公司 線路基板和半導體封裝結構
US10388608B2 (en) * 2015-08-28 2019-08-20 Hitachi Chemical Company, Ltd. Semiconductor device and method for manufacturing same
KR102031404B1 (ko) * 2016-03-31 2019-10-11 주식회사 엘지화학 리버스 오프셋 행오버 중간체 및 이를 형성하는 리버스 오프셋 금속 패턴의 제조방법
JP6418200B2 (ja) 2016-05-31 2018-11-07 日亜化学工業株式会社 発光装置及びその製造方法
JP6649308B2 (ja) * 2017-03-22 2020-02-19 キオクシア株式会社 半導体装置およびその製造方法
KR101971493B1 (ko) * 2017-09-29 2019-04-23 서울과학기술대학교 산학협력단 은코팅 구리 필라 접합 구조체 및 이를 이용한 접합 방법
US11335634B2 (en) * 2019-08-30 2022-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
FR3103315B1 (fr) * 2019-11-19 2021-12-03 St Microelectronics Tours Sas Procédé de fabrication de puces électroniques
FR3104316B1 (fr) * 2019-12-04 2021-12-17 St Microelectronics Tours Sas Procédé de fabrication de puces électroniques
FR3104315B1 (fr) * 2019-12-04 2021-12-17 St Microelectronics Tours Sas Procédé de fabrication de puces électroniques
FR3104317A1 (fr) 2019-12-04 2021-06-11 Stmicroelectronics (Tours) Sas Procédé de fabrication de puces électroniques
JP7078863B2 (ja) * 2020-04-01 2022-06-01 日亜化学工業株式会社 発光装置及びその製造方法
KR20220031398A (ko) * 2020-09-04 2022-03-11 삼성전기주식회사 인쇄회로기판
KR20230145844A (ko) * 2022-04-11 2023-10-18 엘지이노텍 주식회사 회로기판 및 이를 포함하는 반도체 패키지

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4016984B2 (ja) * 2004-12-21 2007-12-05 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、回路基板、及び電子機器
US7425507B2 (en) * 2005-06-28 2008-09-16 Micron Technology, Inc. Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
JP2007036571A (ja) * 2005-07-26 2007-02-08 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP4533283B2 (ja) * 2005-08-29 2010-09-01 新光電気工業株式会社 半導体装置の製造方法
JP5222459B2 (ja) * 2005-10-18 2013-06-26 新光電気工業株式会社 半導体チップの製造方法、マルチチップパッケージ
JP5193503B2 (ja) * 2007-06-04 2013-05-08 新光電気工業株式会社 貫通電極付き基板及びその製造方法
US7791159B2 (en) * 2007-10-30 2010-09-07 Panasonic Corporation Solid-state imaging device and method for fabricating the same
JP5318634B2 (ja) * 2009-03-30 2013-10-16 ラピスセミコンダクタ株式会社 チップサイズパッケージ状の半導体チップ及び製造方法

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US8987902B2 (en) 2015-03-24
JP2013131720A (ja) 2013-07-04
US20130161813A1 (en) 2013-06-27

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