JP5835166B2 - 半導体装置、半導体装置の製造方法 - Google Patents
半導体装置、半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5835166B2 JP5835166B2 JP2012196835A JP2012196835A JP5835166B2 JP 5835166 B2 JP5835166 B2 JP 5835166B2 JP 2012196835 A JP2012196835 A JP 2012196835A JP 2012196835 A JP2012196835 A JP 2012196835A JP 5835166 B2 JP5835166 B2 JP 5835166B2
- Authority
- JP
- Japan
- Prior art keywords
- control board
- control
- semiconductor device
- substrate
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
図1は、本発明の実施の形態1に係る半導体装置の断面図である。本発明の実施の形態1に係る半導体装置10は絶縁基板12を備えている。絶縁基板12は表面に導体の配線パターンを形成できる絶縁材料で形成されている。絶縁基板12の表面側には配線パターン14、16、18が形成されている。絶縁基板12の裏面側には配線パターン20が形成されている。配線パターン16には例えばはんだにより半導体チップ30が固定されている。これにより、半導体チップ30は配線パターン16を介して絶縁基板12に固定されている。
本発明の実施の形態2に係る半導体装置と半導体装置の製造方法は、実施の形態1との共通点が多いので実施の形態1との相違点を中心に説明する。図6は、本発明の実施の形態2に係る半導体装置の断面図である。
本発明の実施の形態3に係る半導体装置と半導体装置の製造方法は、実施の形態1との共通点が多いので実施の形態1との相違点を中心に説明する。図7は、本発明の実施の形態3に係る半導体装置の断面図である。
Claims (7)
- 絶縁基板と、
前記絶縁基板に固定された半導体チップと、
前記半導体チップに電気的に接続された第1制御基板と、
前記第1制御基板から見て前記絶縁基板と反対側に配置された第2制御基板と、
前記第1制御基板と前記第2制御基板の間の電気信号の伝送に用いられる、前記第1制御基板と前記第2制御基板を電気的に接続する制御基板間ワイヤと、
前記絶縁基板、前記第1制御基板、及び前記第2制御基板を、前記絶縁基板の上方に前記第1制御基板が位置し、前記第1制御基板の上方に前記第2制御基板が位置するように収容するケースと、
前記ケースの内壁に固定され前記ケースの中央方向に伸びる垂直部と、前記垂直部に接続され前記絶縁基板と反対の方向に伸びる棒状部とを有する延伸部と、を備え、
前記第1制御基板と前記第2制御基板は前記延伸部によって支持されたことを特徴とする半導体装置。 - 前記絶縁基板上に形成された配線パターンと、
前記半導体チップと前記配線パターンを電気的に接続する配線用ワイヤと、
前記配線パターンと前記第1制御基板を電気的に接続する接続用ワイヤと、を備えたことを特徴とする請求項1に記載の半導体装置。 - 前記ケースに固定され、金属で形成された中継端子と、
前記半導体チップと前記中継端子を電気的に接続する中継端子配線用ワイヤと、
前記中継端子と前記第1制御基板を電気的に接続する中継端子接続用ワイヤと、を備えたことを特徴とする請求項1に記載の半導体装置。 - 前記半導体チップと前記第1制御基板を電気的に接続する直接接続ワイヤを備えたことを特徴とする請求項1に記載の半導体装置。
- 前記棒状部は、前記垂直部に接続された幅太部と、前記幅太部に接続された幅細部と、を有し、
前記第1制御基板は前記垂直部の上に乗せられ、前記第2制御基板は前記幅太部と前記幅細部の段差部分に乗せられたことを特徴とする請求項1〜4のいずれか1項に記載の半導体装置。 - ワイヤによって前記第2制御基板に接続された第3制御基板を備え、
前記第3制御基板は前記幅細部の先端に乗せられたことを特徴とする請求項5に記載の半導体装置。 - 第1制御基板と、第2制御基板と、半導体チップが固定された絶縁基板とを平面的に並べる工程と、
前記第1制御基板、前記第2制御基板、及び前記絶縁基板が平面的に並んだ状態で、 前記第1制御基板、前記第2制御基板、及び前記半導体チップを電気的に接続するために、前記第1制御基板、前記第2制御基板、及び前記半導体チップにワイヤボンディングを施すワイヤボンディング工程と、
前記ワイヤボンディング工程後に、前記第1制御基板、前記第2制御基板、及び前記絶縁基板をケースに収容する工程と、を備え、
前記第1制御基板と前記第2制御基板は、前記ケースの内壁に固定され前記ケースの中央方向に伸びる垂直部と、前記垂直部に接続され前記絶縁基板と反対の方向に伸びる棒状部とを有する延伸部によって支持されたことを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012196835A JP5835166B2 (ja) | 2012-09-07 | 2012-09-07 | 半導体装置、半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012196835A JP5835166B2 (ja) | 2012-09-07 | 2012-09-07 | 半導体装置、半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014053449A JP2014053449A (ja) | 2014-03-20 |
JP5835166B2 true JP5835166B2 (ja) | 2015-12-24 |
Family
ID=50611658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012196835A Active JP5835166B2 (ja) | 2012-09-07 | 2012-09-07 | 半導体装置、半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5835166B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106663676B (zh) * | 2014-08-29 | 2019-05-28 | 三菱电机株式会社 | 半导体装置以及多相用半导体装置 |
JP6455364B2 (ja) * | 2015-08-28 | 2019-01-23 | 三菱電機株式会社 | 半導体装置、インテリジェントパワーモジュールおよび電力変換装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2536624A1 (fr) * | 1982-11-24 | 1984-05-25 | Sev Alternateurs | Procede d'implantation d'un circuit electrique et/ou electronique a l'interieur d'un boitier, circuit et boitier obtenus par le procede |
JPH075660Y2 (ja) * | 1990-11-16 | 1995-02-08 | 菊水電子工業株式会社 | プリント基板支持装置 |
JPH0644193U (ja) * | 1992-11-16 | 1994-06-10 | 株式会社日本電子 | キャビネットにおけるプリント基板の止着構造 |
JP3175584B2 (ja) * | 1996-04-15 | 2001-06-11 | 松下電器産業株式会社 | パワー制御装置 |
JP2002261417A (ja) * | 2001-03-02 | 2002-09-13 | Denso Corp | 混成集積回路装置 |
JP2002271058A (ja) * | 2001-03-09 | 2002-09-20 | Denso Corp | 複数の配線基板を有する電子回路装置 |
DE10214953A1 (de) * | 2002-04-04 | 2003-10-30 | Infineon Technologies Ag | Leistungsmodul mit mindestens zwei Substraten und Verfahren zu seiner Herstellung |
JP4064741B2 (ja) * | 2002-06-25 | 2008-03-19 | 株式会社日立製作所 | 半導体装置 |
JP2006165409A (ja) * | 2004-12-10 | 2006-06-22 | Hitachi Ltd | 電力変換装置 |
-
2012
- 2012-09-07 JP JP2012196835A patent/JP5835166B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2014053449A (ja) | 2014-03-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4264375B2 (ja) | パワー半導体モジュール | |
US8278750B2 (en) | Heat conduction board and mounting method of electronic components | |
JP2006287101A (ja) | パワーモジュール、及び、その製造方法 | |
JP6275292B1 (ja) | 半導体装置及びその製造方法 | |
US9337612B2 (en) | Laser component and method for its production | |
JP4979998B2 (ja) | コネクタ | |
JP5835166B2 (ja) | 半導体装置、半導体装置の製造方法 | |
JP2005142189A (ja) | 半導体装置 | |
JP4524229B2 (ja) | 電装モジュール及び電装ユニット | |
KR100407751B1 (ko) | 반도체장치 | |
JP2008166275A (ja) | 電気的なコネクタストリップ | |
US9425522B2 (en) | Circuit board connector | |
JP2010182828A (ja) | 電力用半導体モジュールとその製造方法 | |
JP6255116B1 (ja) | 半導体装置 | |
JP6443265B2 (ja) | 実装基板 | |
JP4622646B2 (ja) | 半導体装置 | |
JP5732996B2 (ja) | 電気接続箱 | |
JP5048627B2 (ja) | リードフレーム及び半導体装置 | |
JP2014022486A (ja) | ワイヤボンディング構造、及びその製造方法 | |
US9125308B2 (en) | Semiconductor device and method of manufacturing thereof | |
JP3161640U (ja) | ユニバーサル基板 | |
JP2003068963A (ja) | 電子部品搭載構造 | |
JP2016012591A (ja) | 電子回路体およびその製造方法 | |
JP5573543B2 (ja) | 回路構成体及び電気接続箱 | |
JP2020503688A (ja) | 半導体チップを接続する第1および第2接続要素を備えた半導体モジュールおよび製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20141027 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150225 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150317 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150408 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20151006 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20151019 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5835166 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |