JP5739210B2 - 半導体構造体及びその製造方法 - Google Patents
半導体構造体及びその製造方法 Download PDFInfo
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- JP5739210B2 JP5739210B2 JP2011085201A JP2011085201A JP5739210B2 JP 5739210 B2 JP5739210 B2 JP 5739210B2 JP 2011085201 A JP2011085201 A JP 2011085201A JP 2011085201 A JP2011085201 A JP 2011085201A JP 5739210 B2 JP5739210 B2 JP 5739210B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/01—Manufacture or treatment
- H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
- H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/62—Capacitors having potential barriers
- H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
- H10D1/665—Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
- Power Engineering (AREA)
Description
10 ハンドル基板
17 第1マスク層
20 埋め込み型絶縁層
27 第2マスク層
30 半導体層
32、42 ゲート誘電体
33、43 プレーナ・ソース領域
35、45 ボディ領域
36、46 誘電体ゲート・スペーサ
37、47 プレーナ・ドレイン領域
38、48 誘電体ゲートキャップ
40 パッド層
50 ノード誘電体
53、63 レイズド・ソース領域
57,67 レイズド・ドレイン領域
60 導電性トレンチ充填領域
73,83 ソース側金属半導体合金
74,84 ゲート側金属半導体合金
77,87 ドレイン側金属半導体合金
90 誘電体層
94 ワード線コンタクト・ビア構造
95 ゲート側コンタクト・ビア構造
96 ドレイン側コンタクト・ビア構造
97 ビット線コンタクト・ビア構造
100A 第1の浅いトレンチ分離領域
100B 第2の浅いトレンチ分離領域
Claims (10)
- アクセス・トランジスタのプレーナ・ソース領域を含む上部半導体層を含むセミコンダクター・オン・インシュレータ(SOI)基板内に配置された深いトレンチと、
前記深いトレンチ内に配置された導電性トレンチ充填領域と、
前記上部半導体層の上面上に配置され前記プレーナ・ソース領域の上面に接触するレイズド・ソース領域と、
前記レイズド・ソース領域及び前記導電性トレンチ充填領域の上面に接触するレイズド・ストラップ領域とを備え、
前記レイズド・ソース領域及び前記レイズド・ストラップ領域が、ドープされた半導体材料で構成され、
前記レイズド・ソース領域の上面及び前記レイズド・ストラップ領域の上面の上に配置されたソース側金属半導体合金部を更に備え、
前記ソース側金属半導体合金部の一部が前記上部半導体層の上面よりも低い、
半導体構造体。 - 前記深いトレンチ内に配置され、前記プレーナ・ソース領域の側壁及び前記導電性トレンチ充填領域の側壁に接触するノード誘電体を更に備える、請求項1に記載の構造体。
- 前記導電性トレンチ充填領域が、前記プレーナ・ソース領域に接触せず、前記ノード誘電体により前記プレーナ・ソース領域から横方向に隔てられている、請求項2に記載の構造体。
- 前記ノード誘電体が、前記深いトレンチの底面から前記SOI基板の埋め込み型絶縁層の上面よりも上まで垂直方向に延びている、請求項2に記載の構造体。
- 前記レイズド・ソース領域が、前記ドープされた半導体材料の単結晶領域であり、そして前記レイズド・ストラップ領域が、前記ドープされた半導体材料の多結晶領域である、請求項1に記載の構造体。
- 前記レイズド・ソース領域のプレーナ部分は第1の厚さを有し、そして前記レイズド・ストラップ領域のプレーナ部分は第2の厚さを有し、前記第1の厚さが前記第2の厚さよりも厚い、請求項1に記載の構造体。
- 前記アクセス・トランジスタのプレーナ・ドレイン領域上に配置されたレイズド・ドレイン領域を更に備え、前記レイズド・ドレイン領域のプレーナ部分は前記第1の厚さを有する、請求項6に記載の構造体。
- 前記導電性トレンチ充填領域の上部が、前記レイズド・ストラップ領域に接触するドープされた半導体材料で構成されている、請求項1に記載の構造体。
- 前記アクセス・トランジスタのボディ部が、第1導電型のドーピングを有する半導体材料で構成され、前記プレーナ・ソース領域、前記レイズド・ソース領域及び前記レイズド・ストラップ領域のそれぞれが前記第1導電型と反対導電型の第2導電型のドーピングを有する、請求項1に記載の構造体。
- 誘電体材料の浅いトレンチ分離構造を更に備え、前記浅いトレンチ分離構造の外側側壁が前記ノード誘電体の一部及び前記導電性トレンチ充填領域の上部により前記プレーナ・ソース領域から横方向に隔離されている、請求項2に記載の構造体。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/776829 | 2010-05-10 | ||
US12/776,829 US8455875B2 (en) | 2010-05-10 | 2010-05-10 | Embedded DRAM for extremely thin semiconductor-on-insulator |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011238905A JP2011238905A (ja) | 2011-11-24 |
JP5739210B2 true JP5739210B2 (ja) | 2015-06-24 |
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Application Number | Title | Priority Date | Filing Date |
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JP2011085201A Expired - Fee Related JP5739210B2 (ja) | 2010-05-10 | 2011-04-07 | 半導体構造体及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8455875B2 (ja) |
JP (1) | JP5739210B2 (ja) |
KR (1) | KR20110124142A (ja) |
Families Citing this family (24)
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US8546228B2 (en) | 2010-06-16 | 2013-10-01 | International Business Machines Corporation | Strained thin body CMOS device having vertically raised source/drain stressors with single spacer |
CN102299072A (zh) * | 2010-06-24 | 2011-12-28 | 上海华虹Nec电子有限公司 | 沟槽型超级结器件的制作方法及得到的器件 |
US8477526B2 (en) * | 2011-04-27 | 2013-07-02 | Robert Newton Rountree | Low noise memory array |
US20120302030A1 (en) * | 2011-05-29 | 2012-11-29 | Hsiu-Chun Lee | Method of fabricating a deep trench device |
US8507915B2 (en) * | 2011-11-30 | 2013-08-13 | International Business Machines Corporation | Low resistance embedded strap for a trench capacitor |
US8575670B2 (en) * | 2011-12-09 | 2013-11-05 | International Business Machines Corporation | Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate |
US8994085B2 (en) | 2012-01-06 | 2015-03-31 | International Business Machines Corporation | Integrated circuit including DRAM and SRAM/logic |
US8653596B2 (en) * | 2012-01-06 | 2014-02-18 | International Business Machines Corporation | Integrated circuit including DRAM and SRAM/logic |
US8779490B2 (en) * | 2012-07-18 | 2014-07-15 | International Business Machines Corporation | DRAM with dual level word lines |
US8987070B2 (en) * | 2012-09-12 | 2015-03-24 | International Business Machines Corporation | SOI device with embedded liner in box layer to limit STI recess |
US9576964B2 (en) * | 2013-04-05 | 2017-02-21 | International Businesss Machines Corporation | Integrated fin and strap structure for an access transistor of a trench capacitor |
US8889541B1 (en) * | 2013-05-07 | 2014-11-18 | International Business Machines Corporation | Reduced short channel effect of III-V field effect transistor via oxidizing aluminum-rich underlayer |
US9184041B2 (en) * | 2013-06-25 | 2015-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with backside structures to reduce substrate warp |
KR102282195B1 (ko) | 2014-07-16 | 2021-07-27 | 삼성전자 주식회사 | 저항 구조체를 갖는 반도체 장치의 제조 방법 |
US9768254B2 (en) * | 2015-07-30 | 2017-09-19 | International Business Machines Corporation | Leakage-free implantation-free ETSOI transistors |
US9704958B1 (en) * | 2015-12-18 | 2017-07-11 | International Business Machines Corporation | III-V field effect transistor on a dielectric layer |
US10420171B2 (en) * | 2016-08-26 | 2019-09-17 | Qualcomm Incorporated | Semiconductor devices on two sides of an isolation layer |
US9929148B1 (en) * | 2017-02-22 | 2018-03-27 | Globalfoundries Inc. | Semiconductor device including buried capacitive structures and a method of forming the same |
KR101964093B1 (ko) | 2017-08-28 | 2019-04-01 | 한국화학연구원 | 신규 캐소드 버퍼층 소재 및 이를 포함하는 유기광전소자 |
US10559520B2 (en) * | 2017-09-29 | 2020-02-11 | Qualcomm Incorporated | Bulk layer transfer processing with backside silicidation |
US10541242B2 (en) | 2018-05-22 | 2020-01-21 | International Business Machines Corporation | Vertical transistor with eDRAM |
US11069688B2 (en) * | 2018-05-22 | 2021-07-20 | International Business Machines Corporation | Vertical transistor with eDRAM |
CN113178483B (zh) * | 2021-04-27 | 2022-09-02 | 福建省晋华集成电路有限公司 | 一种半导体结构以及半导体结构制备方法 |
CN117529105B (zh) * | 2024-01-08 | 2024-05-14 | 长鑫新桥存储技术有限公司 | 半导体结构及其形成方法 |
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-
2010
- 2010-05-10 US US12/776,829 patent/US8455875B2/en active Active
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2011
- 2011-04-07 JP JP2011085201A patent/JP5739210B2/ja not_active Expired - Fee Related
- 2011-05-04 KR KR1020110042306A patent/KR20110124142A/ko not_active Ceased
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2013
- 2013-03-18 US US13/845,506 patent/US9059213B2/en active Active
Also Published As
Publication number | Publication date |
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US8455875B2 (en) | 2013-06-04 |
US20130230949A1 (en) | 2013-09-05 |
JP2011238905A (ja) | 2011-11-24 |
US20110272762A1 (en) | 2011-11-10 |
KR20110124142A (ko) | 2011-11-16 |
US9059213B2 (en) | 2015-06-16 |
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