JP5717763B2 - 非対称n型電界効果トランジスタおよびこれを形成するための方法 - Google Patents
非対称n型電界効果トランジスタおよびこれを形成するための方法 Download PDFInfo
- Publication number
- JP5717763B2 JP5717763B2 JP2012548085A JP2012548085A JP5717763B2 JP 5717763 B2 JP5717763 B2 JP 5717763B2 JP 2012548085 A JP2012548085 A JP 2012548085A JP 2012548085 A JP2012548085 A JP 2012548085A JP 5717763 B2 JP5717763 B2 JP 5717763B2
- Authority
- JP
- Japan
- Prior art keywords
- implant
- source
- asymmetric
- drain
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
- H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/351—Substrate regions of field-effect devices
- H10D62/357—Substrate regions of field-effect devices of FETs
- H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
- H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
- H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
Landscapes
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/683,634 | 2010-01-07 | ||
| US12/683,634 US8643107B2 (en) | 2010-01-07 | 2010-01-07 | Body-tied asymmetric N-type field effect transistor |
| PCT/US2011/020173 WO2011084975A2 (en) | 2010-01-07 | 2011-01-05 | A body-tied asymmetric n-type field effect transistor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013516793A JP2013516793A (ja) | 2013-05-13 |
| JP2013516793A5 JP2013516793A5 (https=) | 2014-08-14 |
| JP5717763B2 true JP5717763B2 (ja) | 2015-05-13 |
Family
ID=44224203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012548085A Expired - Fee Related JP5717763B2 (ja) | 2010-01-07 | 2011-01-05 | 非対称n型電界効果トランジスタおよびこれを形成するための方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8643107B2 (https=) |
| EP (1) | EP2522032A4 (https=) |
| JP (1) | JP5717763B2 (https=) |
| CN (1) | CN102714222B (https=) |
| WO (1) | WO2011084975A2 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332394A (zh) * | 2011-07-28 | 2012-01-25 | 上海宏力半导体制造有限公司 | 半导体器件、mos晶体管及其形成方法 |
| US8674422B2 (en) * | 2012-01-30 | 2014-03-18 | Synopsys, Inc. | Asymmetric dense floating gate nonvolatile memory with decoupled capacitor |
| US8853761B2 (en) | 2012-01-30 | 2014-10-07 | Synopsys, Inc. | Asymmetric dense floating gate nonvolatile memory with decoupled capacitor |
| US8822278B2 (en) * | 2012-03-29 | 2014-09-02 | International Business Machines Corporation | Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure |
| US9842858B2 (en) | 2015-11-18 | 2017-12-12 | Peregrine Semiconductor Corporation | Butted body contact for SOI transistor |
| US9837965B1 (en) | 2016-09-16 | 2017-12-05 | Peregrine Semiconductor Corporation | Standby voltage condition for fast RF amplifier bias recovery |
| US9960737B1 (en) | 2017-03-06 | 2018-05-01 | Psemi Corporation | Stacked PA power control |
| CN113327983B (zh) * | 2021-05-26 | 2023-05-05 | 武汉新芯集成电路制造有限公司 | 半导体器件及其制造方法 |
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| USH986H (en) * | 1989-06-09 | 1991-11-05 | International Business Machines Corporation | Field effect-transistor with asymmetrical structure |
| US5095348A (en) * | 1989-10-02 | 1992-03-10 | Texas Instruments Incorporated | Semiconductor on insulator transistor |
| US5185280A (en) * | 1991-01-29 | 1993-02-09 | Texas Instruments Incorporated | Method of fabricating a soi transistor with pocket implant and body-to-source (bts) contact |
| USH1435H (en) * | 1991-10-21 | 1995-05-02 | Cherne Richard D | SOI CMOS device having body extension for providing sidewall channel stop and bodytie |
| US5145802A (en) * | 1991-11-12 | 1992-09-08 | United Technologies Corporation | Method of making SOI circuit with buried connectors |
| US5317181A (en) * | 1992-09-10 | 1994-05-31 | United Technologies Corporation | Alternative body contact for fully-depleted silicon-on-insulator transistors |
| US5358879A (en) * | 1993-04-30 | 1994-10-25 | Loral Federal Systems Company | Method of making gate overlapped lightly doped drain for buried channel devices |
| JP3514500B2 (ja) * | 1994-01-28 | 2004-03-31 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
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| US5767549A (en) * | 1996-07-03 | 1998-06-16 | International Business Machines Corporation | SOI CMOS structure |
| US5677224A (en) * | 1996-09-03 | 1997-10-14 | Advanced Micro Devices, Inc. | Method of making asymmetrical N-channel and P-channel devices |
| US6083794A (en) * | 1997-07-10 | 2000-07-04 | International Business Machines Corporation | Method to perform selective drain engineering with a non-critical mask |
| JP3447927B2 (ja) * | 1997-09-19 | 2003-09-16 | 株式会社東芝 | 半導体装置およびその製造方法 |
| US6353245B1 (en) * | 1998-04-09 | 2002-03-05 | Texas Instruments Incorporated | Body-tied-to-source partially depleted SOI MOSFET |
| US6198142B1 (en) * | 1998-07-31 | 2001-03-06 | Intel Corporation | Transistor with minimal junction capacitance and method of fabrication |
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| US6380572B1 (en) * | 1998-10-07 | 2002-04-30 | California Institute Of Technology | Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate |
| US6420761B1 (en) * | 1999-01-20 | 2002-07-16 | International Business Machines Corporation | Asymmetrical semiconductor device for ESD protection |
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| US6268630B1 (en) * | 1999-03-16 | 2001-07-31 | Sandia Corporation | Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications |
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| US6482724B1 (en) * | 1999-09-07 | 2002-11-19 | Texas Instruments Incorporated | Integrated circuit asymmetric transistors |
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| US6667512B1 (en) * | 2000-01-28 | 2003-12-23 | Advanced Micro Devices, Inc. | Asymmetric retrograde halo metal-oxide-semiconductor field-effect transistor (MOSFET) |
| US6274441B1 (en) * | 2000-04-27 | 2001-08-14 | International Business Machines Corporation | Method of forming bitline diffusion halo under gate conductor ledge |
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| JP2002246600A (ja) * | 2001-02-13 | 2002-08-30 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
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| JP4134545B2 (ja) * | 2001-10-02 | 2008-08-20 | 日本電気株式会社 | 半導体装置 |
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| JP3636691B2 (ja) * | 2001-12-26 | 2005-04-06 | 旭化成マイクロシステム株式会社 | 半導体装置の製造方法 |
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| JP2009266868A (ja) * | 2008-04-22 | 2009-11-12 | Oki Semiconductor Co Ltd | Mosfetおよびmosfetの製造方法 |
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-
2010
- 2010-01-07 US US12/683,634 patent/US8643107B2/en active Active
-
2011
- 2011-01-05 JP JP2012548085A patent/JP5717763B2/ja not_active Expired - Fee Related
- 2011-01-05 CN CN201180005602.0A patent/CN102714222B/zh not_active Expired - Fee Related
- 2011-01-05 EP EP11732064.8A patent/EP2522032A4/en not_active Ceased
- 2011-01-05 WO PCT/US2011/020173 patent/WO2011084975A2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP2522032A2 (en) | 2012-11-14 |
| CN102714222A (zh) | 2012-10-03 |
| WO2011084975A3 (en) | 2011-12-29 |
| JP2013516793A (ja) | 2013-05-13 |
| WO2011084975A2 (en) | 2011-07-14 |
| US20110163380A1 (en) | 2011-07-07 |
| US8643107B2 (en) | 2014-02-04 |
| CN102714222B (zh) | 2016-01-27 |
| EP2522032A4 (en) | 2014-05-28 |
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