Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
  • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
  • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
  • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
  • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/351—Substrate regions of field-effect devices
  • H10D62/357—Substrate regions of field-effect devices of FETs
  • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
  • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
  • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask

Definitions

• the exemplary embodiments of this invention relate generally to field effect transistors (FETs) and, more specifically, relate to body-tied FETs.
• microelectronics industry as well as in other industries involving construction of microscopic structures (e.g., micromachines, magnetoresistive heads, etc.) there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a greater amount of circuitry for a given chip size.
• Miniaturization in general allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost.
• Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, FETs and capacitors, for example. Circuit chips with hundreds of millions of such devices are not uncommon. Further size reductions appear to be approaching the physical limit of trace lines and micro-devices that are embedded upon and within their semiconductor substrates.
• the present invention is directed to such micro-sized devices.
• a FET is a transistor having a source, a gate, and a drain.
• the action of the FET depends on the flow of majority carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain, is controlled by the transverse electric field under the gate.
• P-type FETs As known to those skilled in the art, P-type FETs (PFETs) turn ON to allow current flow from source to drain when the gate terminal is at a low or negative potential with respect to the source. When the gate potential is positive or the same as the source, the P-type FET is OFF, and does not conduct current.
• N-type FETs NFETs
• NFETs N-type FETs
• More than one gate can be used to more effectively control the channel.
• the length of the gate determines how fast the FET switches, and can be about the same as the length of the channel (i.e., the distance between the source and drain).
• Multi-gate FETs are considered to be promising candidates to scale complementary metal-oxide semiconductor (CMOS) FET technology down to the sub-22nm regime.
• CMOS complementary metal-oxide semiconductor
• MOS metal-oxide semiconductor
• a FET employing such a channel structure may be referred to as a FinFET.
• CMOS devices were substantially planar along the surface of the semiconductor substrate, the exception being the FET gate that was disposed over the top of the channel. Fins break from this paradigm by using a vertical channel structure in order to maximize the surface area of the channel that is exposed to the gate.
• the gate controls the channel more strongly because it extends over more than one side (surface) of the channel. For example, the gate can enclose three surfaces of the three-dimensional channel, rather than being disposed only across the top surface of the traditional planar channel.
• halo implant may include boron and/or indium.
• SOI Silicon-on-insulator
• the floating body effect is specific to transistors formed on substrates having an insulator layer.
• the neutral floating body is electrically isolated by source/drain and halo extension regions that form oppositely poled diode junctions at the ends of the transistor conduction channel and floating body while the gate electrode is insulated from the conduction channel through a dielectric.
• the insulator layer in the substrate completes insulation of the conduction channel and thus prevents discharge of any charge that may develop in the floating body. Charge injection into the neutral body when the transistor is not conducting develops voltages in the conduction channel in accordance with the source and drain diode characteristics.
• the voltage developed due to charge collection in the channel has the effect of altering the switching threshold of the transistor. This effect, in turn, alters the signal timing and signal propagation speed since any transistor will have a finite slew rate and the rise and fall time of signals is not instantaneous even when gate capacitance is very small. Therefore, the diode characteristics of the source and drain can be tailored to limit charge build-up in the floating body.
• the diode junctions can be made somewhat leaky to allow the floating body of the transistor to be discharged to an acceptable degree.
• FETs are often formed symmetrically with similar or identical source and drain impurity structures, development of such a characteristic reduces the ratio of resistance of the "ON" and "OFF" states of the transistor, often referred to as the on/off ratio.
• a large on/off ratio is generally desirable to support maximum circuit fanout (the number of transistor gates a transistor can drive with acceptable switching speed) and to provide maximum signal voltage swing close to the power supply voltage. Therefore, there is a trade-off between limitation of floating body effects and maintaining a suitable on/off ratio.
• One approach to reduction of floating body effects is to use body contacts to form a connection from the floating body/conduction channel to the source electrode through the impurity well. In some cases, the body contact effectively ties the body of the FET to ground. This approach is only a partial solution since the well can be highly resistive and the connection can be ineffective. Further, the connection requires additional chip space and, therefore, may affect or preclude achievement of the potential integration density that would otherwise be possible.
• This type of device may be referred to as a "body-tied" FET, and may be P-type or N-type.
• asymmetric devices e.g., asymmetric or asymmetrical FETs or MOSFETs
• asymmetric devices there is a preferred direction for majority charge carrier flow.
• this preference may be due to different dopings of or in relation to (i.e., relative to) the source and drain regions, such as different implant dosages or asymmetric implant(s) (e.g., asymmetric source and/or drain extension implants, asymmetric halo implants) relative to the gate channel conductor.
• Asymmetric devices can provide advantages of increased drive currents and reduced parities.
• asymmetric extension and halo devices can be fabricated by using angled implants and by using the (possibly dummy) gate to mask the source or drain region (e.g., due to shadowing by the gate structure).
• an asymmetric N-type field effect transistor comprising: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel.
• a semiconductor device comprising a plurality of asymmetric N-type field effect transistors, where each one of the plurality of asymmetric N-type field effect transistors comprises a source region coupled to a drain region via a channel, a gate structure overlying at least a portion of the channel, a halo implant disposed at least partially in the channel, and a body-tie coupled to the channel, where the halo implant is disposed closer to the source region than the drain region.
• an asymmetric N-type field effect transistor comprising a source region, a drain region, a P-type channel, a halo implant disposed at least partially in the channel, a gate structure and a body-tie, where the halo implant is disposed closer to the source region than the drain region and the asymmetric N- type field effect transistor is operable to act as a symmetric N-type field effect transistor due to the body-tie and asymmetric halo implant.
• a method for forming an asymmetric N- type field effect transistor comprising: forming a source region and a drain region coupled thereto via a channel; forming a gate structure overlying at least a portion of the channel; performing an angled implant to form a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and forming a body-tie coupled to the channel.
• Figure 1 shows a top plan view of an exemplary body-tied asymmetric N-type FET in accordance with the exemplary embodiments of the invention
• Figure 2 shows a cross-sectional view across line A- A' of the exemplary body-tied asymmetric N-type FET shown in Figure 1 ;
• Figure 3 shows a cross-sectional view across line B-B' of the exemplary body-tied asymmetric N-type FET shown in Figure 1 ;
• Figure 4 depicts another exemplary embodiment of a an exemplary body-tied asymmetric N- type FET having asymmetric extension implants and a different disposition of the halo implant; and
• Figure 5 depicts a flowchart illustrating one non-limiting example of a method for practicing the exemplary embodiments of this invention.
• the exemplary embodiments of the invention address the density problem by utilizing a body-tied asymmetric (SOI) NFET. It has been determined that a body-tied asymmetric device no longer performs asymmetrically and, instead, acts as a normal symmetric device. Although the body tie would consume some area, the layout could be packed, for example, by alternating the stack orientation. In dense circuits, for example, the body-tied asymmetric NFET device may be used to create a symmetric device in cases where the groundrule spacing would not otherwise allow for a normal symmetric device (e.g., in the same silicon island).
• SOI body-tied asymmetric
• the source is overlapped more and the drain less (i.e., the drain is underlapped).
• this may be accomplished by using an angled extension implant (e.g., using the gate structure to at least partially mask the drain).
• the drain underlap will drop the effective device Miller capacitance without a substantial resistance penalty, as would occur if the source side was underlapped.
• the overlapped source could drop the total device resistance.
• the angled implant is performed at an angle of 1-89° (relative to a vertical axis, relative to an axis normal to an overall, general surface of the semiconductor device), preferably an angle of about (e.g., approximately, substantially) 10-30°, and even more preferably an angle of about (e.g., approximately, substantially) 20°.
• the implant comprises a zero-degree implant and an angled adder (implant).
• any suitable body-tie structure may be utilized.
• the body-tie may have at least one of the following structures: H-gate, T-gate, Schottky and/or body-source tie.
• any suitable asymmetric implant or doping may be used, such as a halo implant comprising boron and/or indium, as non-limiting examples.
• FIG. 1 shows a top plan view of an exemplary body-tied asymmetric N-type FET 100 in accordance with the exemplary embodiments of the invention.
• the FET 100 has a source region (SR) 102 with a source contact 104 and a drain region (DR) 106 with a drain contact 108 located within an active region 110 of the FET 100.
• the SR 102 and DR 106 are coupled to one another via a channel 1 12. Since this is a N-type FET, the channel 112 is a P-type channel.
• a gate structure (gate) 114 overlies at least a portion of the channel 112. As with a conventional FET, current through the channel 1 12 is controlled by the transverse electric field under the gate 114.
• the FET 100 also includes a body contact 116 for the body-tie.
• the body contact 1 16 is coupled to the channel 112.
• a halo implant (see Halo 124 in Figure 3) is disposed in the channel 1 12 closer to the SR 102 than the DR 106. This asymmetrical doping may be accomplished via an angled implant (e.g., an angled halo implant) that uses the gate 114 to at least partially mask the DR 106.
• the body-tie e.g., via the body contact 116) may be used to apply any desired bias in order to control the body potential (e.g., the accumulation and/or discharge of charge built up in the channel/floating body). As a non- limiting example, the body-tie may be connected to ground.
• the FET 100 optionally may include source and/or drain extension implants. These will be described in further detail below in reference to Figure 3.
• Figure 2 shows a cross-sectional view across line A-A' of the exemplary body-tied asymmetric N-type FET 100 shown in Figure 1.
• the FET 100 also includes a shallow trench isolation (STI) 118.
• the FET 100 overlies (e.g., is disposed on) a buried oxide layer 120.
• the buried oxide layer 120 overlies a substrate 122 (e.g., a silicon substrate).
• Figure 3 shows a cross-sectional view across line B-B' of the exemplary body-tied asymmetric N-type FET 100 shown in Figure 1.
• the halo implant (halo) 124 is clearly visible.
• the halo 124 may be located (e.g., disposed) at least partially within the channel 112.
• the halo 124 may be formed using an angled halo implant 126.
• the angled halo implant 126 may be at an angle of 1 -89° (relative to a vertical axis, relative to an axis normal to an overall, general surface of the FET 100), preferably an angle of about (e.g., approximately, substantially) 10- 30°, and even more preferably an angle of about (e.g., approximately, substantially) 20°.
• the angled halo implant 126 may utilize the gate 114 in order to at least partially mask the DR 106 from the angled halo implant 126. This results in the FET 100 being asymmetric since the halo 124 is disposed closer to the SR 102 than the DR 106.
• the FET 100 optionally may include source and/or drain extension implants (SE 128 and DE 130, respectively).
• These extension implants may be formed using an angled implant (e.g., at an angle of 1-89° (relative to a vertical axis, relative to an axis normal to an overall, general surface of the FET 100)).
• an angled implant may utilize the gate 1 14 in order to at least partially mask the DR 106 from the angled implant (e.g., 126).
• the SE 128 and DE 130 shown in Figure 3 are symmetric (e.g., in size and/or doping).
• the halo 124 is disposed entirely within the channel 112.
• the source/drain extension implants are symmetric (e.g., SE 128 and DE 130), they may be formed using a vertical implant as opposed to an angled implant.
• Figure 4 depicts another exemplary body-tied asymmetric N-type FET 200 in accordance with the exemplary embodiments of the invention.
• the FET 200 has asymmetric extension implants and a different disposition of the halo implant.
• the source extension implant (SE) 228 is larger than the drain extension implant (DE) 130.
• the SE 228 may be said to overlap the gate 1 14 while the DE 130 underlaps the gate 1 14.
• the halo implant (halo) 224 is partially disposed in the SR 102.
• exemplary embodiments of the invention may include asymmetric source/drain extension implants with the halo implant entirely disposed within the channel.
• still further exemplary embodiments of the invention may include symmetric source/drain extension implants with the halo implant partially disposed within the source region.
• the halo implant may comprise (e.g., be doped with) one or more of B, BF 2 and In.
• the source/drain regions may comprise (e.g., be doped with) one or more of As and P.
• the source/drain extension implants may comprise (e.g., be doped with) one or more of As and P.
• One feature of the exemplary body-tied asymmetric N-type FET 100 described above in relation to Figures 1 -4 is that although the FET 100 is asymmetric (due to the doping), the FET 100 acts as a symmetric FET. This is due to the body-tie and asymmetrical doping (i.e., the halo implant 124).
• the symmetric operation of the asymmetric FET 100 provides a number of advantages.
• the asymmetric FET 100 may be used to create a symmetric device in cases where the groundrule spacing would not otherwise allow for a normal symmetric device (e.g., in the same silicon island).
• a semiconductor device may include a plurality of asymmetric FETs 100 without the necessity for also including symmetric FETs.
• the patterning and formation of the semiconductor device can be simplified (e.g., fewer masks, fewer operations), for example, because there is no longer a need to mask the symmetric FETs while operations are performed on the asymmetric FETs (and vice versa). This can lead to cost savings and increased efficiency (e.g., at least with respect to production and production costs).
• an asymmetric N-type field effect transistor comprising: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel.
• a FET as in any above, where the halo implant is partially disposed in the source region.
• a FET as in any above, where the insulator layer comprises a buried oxide layer.
• a FET as in any above, where the substrate comprises silicon.
• a FET as in any above, where the angled implant procedure comprises performing an angled implant at an angle of substantially (approximately) 20 degrees from a vertical axis (an axis that is normal to a horizontal surface of the asymmetric N-type field effect transistor).
• the body-tie comprises at least one of: an H-gate, a T-gate, a Schottky structure and a body-source tie.
• the halo implant comprises at least one of boron and indium.
• the asymmetric N-type field effect transistor comprises an asymmetric silicon-on-insulator N-type field effect transistor.
• the source extension implant and drain extension implant are symmetric (e.g., have a similar size and/or a similar doping).
• the source extension implant and drain extension implant are asymmetric (e.g., have different sizes and/or different doping).
• a semiconductor device comprising a plurality of asymmetric N-type field effect transistors, where each one of the plurality of asymmetric retype field effect transistors comprises a source region coupled to a drain region via a channel, a gate structure overlying at least a portion of the channel, a halo implant disposed at least partially in the channel, and a body-tie coupled to the channel, where the halo implant is disposed closer to the source region than the drain region.
• an asymmetric N-type field effect transistor comprising a source region, a drain region, a P-type channel, a halo implant disposed at least partially in the channel, a gate structure and a body-tie, where the halo implant is disposed closer to the source region than the drain region, where the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor due to the body-tie and asymmetric halo implant.
• a method for forming an asymmetric N-type field effect transistor comprising: forming a source region and a drain region coupled thereto via a channel (501); forming a gate structure overlying at least a portion of the channel (502); performing an angled implant to form a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region (503); and forming a body-tie coupled to the channel (504).
• the angled implant uses at least a portion of the gate structure to at least partially mask the drain region.
• the blocks shown in Figure 5 further may be considered to correspond to one or more functions and/or operations that are performed by one or more components, circuits, chips, apparatus, processors, computer programs and/or function blocks. Any and/or all of the above may be implemented in any practicable solution or arrangement that enables operation in accordance with the exemplary embodiments of the invention as described herein.
• the arrangement of the blocks depicted in Figure 5 should be considered merely exemplary and non-limiting. It should be appreciated that the blocks shown in Figure 5 may correspond to one or more functions and/or operations that may be performed in any order (e.g., any suitable, practicable and/or feasible order) and/or concurrently (e.g., as suitable, practicable and/or feasible) so as to implement one or more of the exemplary embodiments of the invention. In addition, one or more additional functions, operations and/or steps may be utilized in conjunction with those shown in Figure 5 so as to implement one or more further exemplary embodiments of the invention.
• such formation may involve the deposition and/or etching of various materials and layers.
• such formation may utilize photolithographic materials and/or techniques, such as one or more masks (e.g., hard masks, soft masks), photosensitive materials (e.g., photoresist), antireflective coatings and planarization layers.
• photolithographic materials and/or techniques such as one or more masks (e.g., hard masks, soft masks), photosensitive materials (e.g., photoresist), antireflective coatings and planarization layers.
• Depositing the materials may include any now known or later developed techniques appropriate for the material to be deposited, including, but not limited to: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating or evaporation.
• CVD chemical vapor deposition
• LPCVD low-pressure CVD
• PECVD plasma-enhanced CVD
• SACVD semi-at
• connection or coupling between the identified elements may be, as non-limiting examples, physical, electrical, magnetic, logical or any suitable combination thereof in accordance with the described exemplary embodiments.
• connection or coupling may comprise one or more printed electrical connections, wires, cables, mediums or any suitable combination thereof.
• various exemplary embodiments of the invention can be implemented in different mediums, such as software, hardware, logic, special purpose circuits or any combination thereof.
• some aspects may be implemented in software which may be run on a computing device, while other aspects may be implemented in hardware.

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