JP5700927B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP5700927B2 JP5700927B2 JP2009266485A JP2009266485A JP5700927B2 JP 5700927 B2 JP5700927 B2 JP 5700927B2 JP 2009266485 A JP2009266485 A JP 2009266485A JP 2009266485 A JP2009266485 A JP 2009266485A JP 5700927 B2 JP5700927 B2 JP 5700927B2
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- chip
- resin
- bonding wire
- sealing
- semiconductor chip
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- H—ELECTRICITY
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- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/453—Leadframes comprising flexible metallic tapes
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- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
- H10W70/424—Cross-sectional shapes
- H10W70/427—Bent parts
- H10W70/429—Bent parts being the outer leads
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/019—Manufacture or treatment using temporary auxiliary substrates
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- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
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- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
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- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
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- H—ELECTRICITY
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- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/521—Structures or relative sizes of bond wires
- H10W72/522—Multilayered bond wires, e.g. having a coating concentric around a core
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/533—Cross-sectional shape
- H10W72/534—Cross-sectional shape being rectangular
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- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
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- H—ELECTRICITY
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- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
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- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
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- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
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- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/555—Materials of bond wires of outermost layers of multilayered bond wires, e.g. material of a coating
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
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- H—ELECTRICITY
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- H10W72/00—Interconnections or connectors in packages
- H10W72/834—Interconnections on sidewalls of chips
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- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
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- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9413—Dispositions of bond pads on encapsulations
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009266485A JP5700927B2 (ja) | 2008-11-28 | 2009-11-24 | 半導体装置及び半導体装置の製造方法 |
| US12/626,069 US8394678B2 (en) | 2008-11-28 | 2009-11-25 | Semiconductor chip stacked body and method of manufacturing the same |
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008305187 | 2008-11-28 | ||
| JP2008305187 | 2008-11-28 | ||
| JP2009010828 | 2009-01-21 | ||
| JP2009010828 | 2009-01-21 | ||
| JP2009149116 | 2009-06-23 | ||
| JP2009149116 | 2009-06-23 | ||
| JP2009266485A JP5700927B2 (ja) | 2008-11-28 | 2009-11-24 | 半導体装置及び半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011029581A JP2011029581A (ja) | 2011-02-10 |
| JP2011029581A5 JP2011029581A5 (https=) | 2012-12-06 |
| JP5700927B2 true JP5700927B2 (ja) | 2015-04-15 |
Family
ID=42222015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009266485A Expired - Fee Related JP5700927B2 (ja) | 2008-11-28 | 2009-11-24 | 半導体装置及び半導体装置の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8394678B2 (https=) |
| JP (1) | JP5700927B2 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4776675B2 (ja) | 2008-10-31 | 2011-09-21 | 株式会社東芝 | 半導体メモリカード |
| MY152355A (en) | 2011-04-11 | 2014-09-15 | Carsem M Sdn Bhd | Short and low loop wire bonding |
| CN108269792A (zh) * | 2011-05-18 | 2018-07-10 | 晟碟半导体(上海)有限公司 | 瀑布引线键合 |
| KR20120135626A (ko) * | 2011-06-07 | 2012-12-17 | 삼성전자주식회사 | 반도체 칩 패키지의 제조 방법 |
| MY181180A (en) | 2011-09-09 | 2020-12-21 | Carsem M Sdn Bhd | Low loop wire bonding |
| US9595487B2 (en) * | 2013-06-25 | 2017-03-14 | Infineon Technologies Ag | Circuit arrangement and method for manufacturing the same |
| CN106686932B (zh) | 2015-11-05 | 2019-12-13 | 精能医学股份有限公司 | 植入式电子装置的防水结构 |
| FR3048123B1 (fr) * | 2016-02-19 | 2018-11-16 | 3D Plus | Procede d'interconnexion chip on chip miniaturisee d'un module electronique 3d |
| US10923456B2 (en) * | 2018-12-20 | 2021-02-16 | Cerebras Systems Inc. | Systems and methods for hierarchical exposure of an integrated circuit having multiple interconnected die |
| JP7494067B2 (ja) | 2020-09-14 | 2024-06-03 | キオクシア株式会社 | 半導体装置の製造方法、及び半導体製造装置 |
| CN113851397B (zh) * | 2021-09-07 | 2025-06-10 | 长江存储科技有限责任公司 | 一种堆叠封装芯片的开封方法 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5675180A (en) | 1994-06-23 | 1997-10-07 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments |
| JP3847432B2 (ja) * | 1997-12-25 | 2006-11-22 | 沖電気工業株式会社 | 樹脂封止半導体装置及びその製造方法 |
| US6207474B1 (en) * | 1998-03-09 | 2001-03-27 | Micron Technology, Inc. | Method of forming a stack of packaged memory die and resulting apparatus |
| US6291894B1 (en) * | 1998-08-31 | 2001-09-18 | Micron Technology, Inc. | Method and apparatus for a semiconductor package for vertical surface mounting |
| JP3476383B2 (ja) * | 1999-05-27 | 2003-12-10 | シャープ株式会社 | 半導体積層パッケージ |
| JP2001156250A (ja) * | 1999-11-24 | 2001-06-08 | Seiko Epson Corp | 半導体チップ、マルチチップパッケージ,および半導体装置と、並びに、それを用いた電子機器 |
| JP4361670B2 (ja) * | 2000-08-02 | 2009-11-11 | 富士通マイクロエレクトロニクス株式会社 | 半導体素子積層体、半導体素子積層体の製造方法、及び半導体装置 |
| JP2005191342A (ja) * | 2003-12-26 | 2005-07-14 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP4398305B2 (ja) * | 2004-06-02 | 2010-01-13 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
| US20070158807A1 (en) * | 2005-12-29 | 2007-07-12 | Daoqiang Lu | Edge interconnects for die stacking |
| US8723332B2 (en) * | 2007-06-11 | 2014-05-13 | Invensas Corporation | Electrically interconnected stacked die assemblies |
| US7892894B2 (en) * | 2007-09-20 | 2011-02-22 | Stats Chippac Ltd. | Method of manufacturing integrated circuit package system with warp-free chip |
| US7843046B2 (en) * | 2008-02-19 | 2010-11-30 | Vertical Circuits, Inc. | Flat leadless packages and stacked leadless package assemblies |
-
2009
- 2009-11-24 JP JP2009266485A patent/JP5700927B2/ja not_active Expired - Fee Related
- 2009-11-25 US US12/626,069 patent/US8394678B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20100133677A1 (en) | 2010-06-03 |
| US8394678B2 (en) | 2013-03-12 |
| JP2011029581A (ja) | 2011-02-10 |
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