JP5700563B2 - 半導体素子構造の形成方法、及び半導体素子 - Google Patents
半導体素子構造の形成方法、及び半導体素子 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 199
- 238000000034 method Methods 0.000 title claims description 50
- 239000010410 layer Substances 0.000 claims description 183
- 238000005468 ion implantation Methods 0.000 claims description 49
- 150000002500 ions Chemical class 0.000 claims description 28
- 239000011247 coating layer Substances 0.000 claims description 22
- 238000009826 distribution Methods 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 239000002356 single layer Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000002040 relaxant effect Effects 0.000 claims description 2
- 238000001069 Raman spectroscopy Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 230000001133 acceleration Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- 238000005259 measurement Methods 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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- H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
- H01L21/786—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
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- H01—ELECTRIC ELEMENTS
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Description
しかし(11)の発明によれば、イオン注入の後にアニールを行うことで、半導体層の損傷が回復し、半導体素子の機能低下を抑制できる。
前記半導体層は、前記所定箇所の一部又は全部を含み且つ前記ゲート絶縁層に被覆されていない箇所に所定距離だけ延在する歪み層と、前記歪み層を挟んで位置する緩和層と、を有する半導体素子。
21 歪半導体層
23,25 緩和半導体層
30 被覆層
40 絶縁酸化膜
50 基板
Claims (16)
- 被覆層が一部に施された歪半導体層を絶縁酸化膜上に有する基板の面上よりイオン注入を行い、前記被覆層で遮蔽された歪半導体層の歪状態を維持する一方、前記被覆層で遮蔽されていない歪半導体層の歪状態を緩和し緩和半導体層へと変化させることで、前記歪状態を維持した前記歪半導体層と、前記緩和半導体層との間にヘテロ接合を形成するヘテロ接合形成工程を有する半導体素子構造の形成方法であって、
前記被覆層は、前記半導体の酸化物で構成される酸化膜と、前記酸化膜を被覆するゲート電極とを有し、
前記方法は、前記イオンの反跳エネルギ分布のピークが、前記歪半導体層と前記絶縁酸化膜との界面に理論的に位置するようにエネルギを調節する、半導体素子構造の形成方法。 - 前記被覆層は、前記歪半導体層より高い又は低い熱膨張率の素材からなる単層構造を備える請求項1記載の形成方法。
- 前記イオン注入は、ドーパントを除く元素を主成分とする又はこの元素からなるイオンの注入である請求項1又は2記載の形成方法。
- 前記イオン注入は、前記絶縁酸化膜及び前記歪半導体層を構成する元素を主成分とする又はこの元素からなるイオンの注入である請求項1から3いずれか記載の形成方法。
- 前記歪半導体層は、Si又はSiGeで構成される請求項1から4いずれか記載の形成方法。
- 前記歪半導体層は、引張り歪みSi、又は圧縮歪みSiGeで構成される請求項5記載の形成方法。
- 前記イオン注入は、O、Si及びGeからなる群より選ばれる1種以上の元素を主成分とする又はこの元素からなるイオンの注入である請求項5又は6記載の形成方法。
- 前記イオン注入は、H、He、Li、Be及びCからなる群より選ばれる1種以上の元素を主成分とする又はこの元素からなるイオンの注入である請求項5又は6記載の形成方法。
- 前記イオン注入の後に行うアニール工程を更に有する請求項1から8いずれか記載の形成方法。
- 前記イオン注入は、前記歪半導体層の表面に対して直交する方向から所定角度をなす方向で行う請求項1から9いずれか記載の形成方法。
- 前記所定角度に応じて、イオンを注入するエネルギを調節する工程を更に有する請求項10記載の形成方法。
- 前記緩和半導体層、又は前記緩和半導体層及び前記歪半導体層に、不純物をドープすることで、ソース及びドレインを形成する工程を更に有する請求項1から11いずれか記載の形成方法。
- 前記ヘテロ接合形成工程の後、へテロ接合が形成された前記歪半導体層及び前記緩和半導体層に対して、MOSFETの製造工程におけるソース拡散層及びドレイン拡散層に用いるイオンを注入する工程を有する請求項1から12いずれか記載の形成方法。
- 半導体層と、この半導体層の所定箇所上に位置するゲート絶縁膜と、このゲート絶縁膜を被覆するゲート電極と、を備え、
前記半導体層は、前記所定箇所の一部又は全部を含み且つ前記ゲート絶縁層に被覆されていない箇所に所定距離だけ延在する歪み層と、前記歪み層を挟んで位置する緩和層と、を有する半導体素子であって、
前記歪み層と前記緩和層は、同じ半導体からなり、
前記歪み層と前記緩和層との間にヘテロ接合が形成されており、
前記半導体層の前記所定箇所の前記歪み層は、チャネルとして機能し、前記所定箇所から前記所定距離だけ延在する前記歪み層は、ドレインの一部として機能し、前記緩和層は、ソース及び前記一部以外のドレインとして機能しており、
ソース側のヘテロ接合面とチャネルとの距離が、ドレイン側のヘテロ接合面とチャネルとの距離よりも短い、半導体素子。 - 前記半導体層は、Si又はSiGeで構成される請求項14記載の半導体素子。
- 前記半導体層は、引張り歪みSi、又は圧縮歪みSiGeで構成される請求項15記載の半導体素子。
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JP2011530849A JP5700563B2 (ja) | 2009-09-09 | 2010-09-08 | 半導体素子構造の形成方法、及び半導体素子 |
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KR (1) | KR101297397B1 (ja) |
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JPH10209453A (ja) * | 1997-01-17 | 1998-08-07 | Toshiba Corp | 半導体装置およびその製造方法 |
US20060014366A1 (en) * | 2002-06-07 | 2006-01-19 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
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JP2006019727A (ja) * | 2004-06-29 | 2006-01-19 | Internatl Business Mach Corp <Ibm> | 勾配付き組み込みシリコン−ゲルマニウムのソース−ドレイン及び/又は延長部をもつ、歪みp型mosfetの構造及びこれを製造する方法 |
JP2009152391A (ja) * | 2007-12-20 | 2009-07-09 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法及び半導体装置 |
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KR101297397B1 (ko) | 2013-08-19 |
US20120168818A1 (en) | 2012-07-05 |
US8941092B2 (en) | 2015-01-27 |
JPWO2011030782A1 (ja) | 2013-02-07 |
WO2011030782A1 (ja) | 2011-03-17 |
TW201123273A (en) | 2011-07-01 |
KR20120027548A (ko) | 2012-03-21 |
TWI520182B (zh) | 2016-02-01 |
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