JP5680801B1 - 半導体装置の製造方法、及び、半導体装置 - Google Patents
半導体装置の製造方法、及び、半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 172
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 58
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 160
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000009792 diffusion process Methods 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 9
- 150000001875 compounds Chemical class 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 56
- 229910052710 silicon Inorganic materials 0.000 description 56
- 239000010703 silicon Substances 0.000 description 56
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- POFVJRKJJBFPII-UHFFFAOYSA-N N-cyclopentyl-5-[2-[[5-[(4-ethylpiperazin-1-yl)methyl]pyridin-2-yl]amino]-5-fluoropyrimidin-4-yl]-4-methyl-1,3-thiazol-2-amine Chemical compound C1(CCCC1)NC=1SC(=C(N=1)C)C1=NC(=NC=C1F)NC1=NC=C(C=C1)CN1CCN(CC1)CC POFVJRKJJBFPII-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
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Abstract
Description
すなわち、3つのマスクを用いてシリコン柱、平面状シリコン層、ゲート配線を形成している。
シリコン基板101上に形成されたフィン状シリコン層103と、前記フィン状シリコン層103の周囲に形成された第1の絶縁膜104と、前記フィン状シリコン層103上に形成された柱状シリコン層109と、前記柱状シリコン層109のフィン状半導体層に直交する方向の幅は前記フィン状シリコン層103の自身に直交する方向の幅と同じであり、前記柱状シリコン層109の周囲に形成されたゲート絶縁膜120と、前記ゲート絶縁膜120の周囲に形成された金属からなるゲート電極121aと、前記ゲート電極121aに接続された前記フィン状シリコン層109に直交する方向に延在する金属からなるゲート配線121bと、前記ゲート電極121aと前記ゲート配線121bの周囲と底部に形成された前記ゲート絶縁膜120と、前記ゲート電極121aの外側の幅W1と前記ゲート配線121bの幅W2は同じであり、前記柱状シリコン層109の上部に形成された第1の拡散層112と、前記フィン状シリコン層103の上部と前記柱状シリコン層109の下部に形成された第2の拡散層115と、を有する。
102.第1のレジスト
103.フィン状シリコン層
104.第1の絶縁膜
105.第2の絶縁膜
106.第1のポリシリコン、第1のダミーゲート
107.第3の絶縁膜
108.第2のレジスト
109.柱状シリコン層
110.第4の絶縁膜
111.第3のレジスト
112.第1の拡散層
113.第2のポリシリコン、第2のダミーゲート
114.第5の絶縁膜、第5の絶縁膜からなるサイドウォール
115.第2の拡散層
116.金属と半導体の化合物
117.金属と半導体の化合物
118.コンタクトストッパ膜
119.層間絶縁膜
120.ゲート絶縁膜
121.金属
121a.ゲート電極
121b.ゲート配線
122.酸化膜
123.第4のレジスト
124.コンタクト孔
125.コンタクト孔
126.第5のレジスト
127.コンタクト孔
128.金属
129.コンタクト
130.コンタクト
131.コンタクト
132.第6のレジスト
133.第6のレジスト
134.第6のレジスト
135.金属配線
136.金属配線
137.金属配線
Claims (6)
- 半導体基板上にフィン状半導体層を形成し、前記フィン状半導体層の周囲に第1の絶縁膜を形成する第1工程と、
前記第1工程の後、
前記フィン状半導体層の周囲に第2の絶縁膜を形成し、
前記第2の絶縁膜の上に第1のポリシリコンを堆積し平坦化し、
ゲート配線と柱状半導体層を形成するための第2のレジストを、前記フィン状半導体層の方向に対して垂直の方向に形成し、
前記第1のポリシリコンと前記第2の絶縁膜と前記フィン状半導体層をエッチングすることにより、柱状半導体層と前記第1のポリシリコンによる第1のダミーゲートを形成する第2工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第2の絶縁膜の上に第1のポリシリコンを堆積し平坦化後、前記第1のポリシリコン上に第3の絶縁膜を形成することをさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2工程の後、前記柱状半導体層と前記第1のダミーゲートの周囲に第4の絶縁膜を形成し、前記第4の絶縁膜の周囲に第2のポリシリコンを堆積し、エッチングをすることにより、前記第1のダミーゲートと前記柱状半導体層の側壁に残存させ、第2のダミーゲートを形成する第3工程を有することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記柱状半導体層と前記第1のダミーゲートの周囲に第4の絶縁膜を形成後、第3のレジストを形成し、エッチバックを行い、前記柱状半導体層上部を露出し、前記柱状半導体層上部に第1の拡散層を形成することを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記第2のダミーゲートの周囲に、第5の絶縁膜を形成し、エッチングをし、サイドウォール状に残存させ、前記第5の絶縁膜からなるサイドウォールを形成し、前記フィン状半導体層上部と前記柱状半導体層下部に第2の拡散層を形成し、前記第2の拡散層上に金属と半導体の化合物を形成する第4工程を有することを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記第4の工程の後、コンタクトストッパ膜を堆積し、層間絶縁膜を堆積し化学機械研磨し、前記第2のダミーゲートと前記第1のダミーゲートの上部を露出し、前記第2のダミーゲートと前記第1のダミーゲートを除去し、前記第2の絶縁膜と前記第4の絶縁膜を除去し、ゲート絶縁膜を前記柱状半導体層の周囲と前記第5の絶縁膜の内側に形成し、金属を堆積し、エッチバックを行い、ゲート電極及びゲート配線を形成する第5工程を有することを特徴とする請求項5に記載の半導体装置の製造方法。
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