JP5679821B2 - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 134
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims description 349
- 210000000746 body region Anatomy 0.000 claims description 98
- 239000000758 substrate Substances 0.000 claims description 31
- 239000002243 precursor Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 239000010409 thin film Substances 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 12
- 239000000654 additive Substances 0.000 claims description 6
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 121
- 229910010271 silicon carbide Inorganic materials 0.000 description 116
- 239000010410 layer Substances 0.000 description 86
- 230000005684 electric field Effects 0.000 description 32
- 239000011229 interlayer Substances 0.000 description 19
- 230000015572 biosynthetic process Effects 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 12
- 238000007254 oxidation reaction Methods 0.000 description 12
- 238000001994 activation Methods 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 10
- 230000004913 activation Effects 0.000 description 9
- 238000002513 implantation Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 7
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- 230000015556 catabolic process Effects 0.000 description 5
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- 230000005669 field effect Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
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- 238000002347 injection Methods 0.000 description 1
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- 238000009413 insulation Methods 0.000 description 1
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- 238000005121 nitriding Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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Description
本発明の半導体装置を説明する前に、本発明の前提となる半導体装置について説明する。図1は、本発明の前提となる半導体装置1の一部を示す断面図である。図2は、本発明の前提となる他の半導体装置1Aの一部を示す断面図である。図1および図2に示す半導体装置1,1Aは、炭化珪素(SiC)パワーデバイスである。図1および図2には、各半導体装置1,1AのMOSFETとして動作する領域の素子構造の最小単位(以下「素子単位構造」という場合がある)の断面を示している。図1,図2に示す半導体装置1,1Aは、素子単位構造がそれぞれ図1,図2の左右方向に折り返されて連続した構造になっている。
図3は、本発明の実施の一形態である半導体装置30の一部を示す断面図である。本実施の形態の半導体装置30は、炭化珪素(SiC)を用いたSiC半導体装置、より詳細にはSiCパワーデバイスである。図3には、半導体装置30のMOSFETとして動作する領域の素子構造の最小単位(以下「素子単位構造」という場合がある)の断面を示している。本実施の形態の半導体装置30は、この素子単位構造が図3の左右方向に折り返されて連続した構造になっている。
Claims (3)
- SiC半導体基板(31)と、
前記SiC半導体基板(31)の一方側の表面上に設けられる第1導電型SiCドリフト層(32)と、
前記第1導電型SiCドリフト層(32)の表面部に選択的に形成される第2導電型SiCボディ領域(33)と、
前記第2導電型SiCボディ領域(33)内に選択的に形成される第1導電型SiCソース領域(34)と、
前記第1導電型SiCドリフト層(32)の表面部に選択的に形成され、前記第1導電型SiCソース領域(34)から離隔して前記第2導電型SiCボディ領域(33)に隣接し、前記第1導電型SiCドリフト層(32)よりドーピング濃度を高められた第1導電型SiCデプレッション領域(36)と、
前記第1導電型SiCソース領域(34)上、前記第2導電型SiCボディ領域(33)上および前記第1導電型SiCデプレッション領域(36)上にわたって設けられ、シリコン酸化膜またはシリコン酸化窒化膜から成るゲート絶縁膜(37)と、
前記ゲート絶縁膜(37)上に設けられるゲート電極(38,61,71,81)とを備え、
前記ゲート電極(38,61,71,81)は、前記第1導電型SiCソース領域(34)の一部分、前記第2導電型SiCボディ領域(33)および前記第1導電型SiCデプレッション領域(36)の一部分を覆うように前記ゲート絶縁膜(37)上に設けられ、前記第1導電型SiCデプレッション領域(36)上に端部を有し、
前記第1導電型SiCデプレッション領域(36)上の前記ゲート電極(38,61,71,81)の端部の位置における前記ゲート絶縁膜(37)の膜厚は、前記第2導電型SiCボディ領域(33)上における前記ゲート絶縁膜(37)の膜厚よりも大きく、前記第2導電型SiCボディ領域(33)上における前記ゲート絶縁膜(37)の膜厚の1.84倍以上であり、かつ前記第2導電型SiCボディ領域(33)上における前記ゲート電極(38,61,71,81)の膜厚以下であることを特徴とする半導体装置。 - SiC半導体基板(31)の一方側の表面上に第1導電型SiCドリフト層(32)を形成する工程と、
前記第1導電型SiCドリフト層(32)の表面部に、第1導電型SiCソース領域(34)を含む第2導電型SiCボディ領域(33)と、前記第1導電型SiCソース領域(34)から離隔して前記第2導電型SiCボディ領域(33)に隣接し、前記第1導電型SiCドリフト層(32)よりドーピング濃度を高められた第1導電型SiCデプレッション領域(36)とを形成する工程と、
前記第1導電型SiCソース領域(34)上、前記第2導電型SiCボディ領域(33)上および前記第1導電型SiCデプレッション領域(36)上にわたって、シリコン酸化膜またはシリコン酸化窒化膜から成る薄膜絶縁膜(46)を形成する工程と、
前記薄膜絶縁膜(46)上に、前記第1導電型SiCソース領域(34)、前記第2導電型SiCボディ領域(33)および前記第1導電型SiCデプレッション領域(36)を覆うように、ゲート電極(38,61,71,81)となる多結晶シリコン膜を形成する工程と、
前記第1導電型SiCデプレッション領域(36)上に端部を有するように、前記多結晶シリコン膜の一部を除去して、ゲート電極前駆体(47)を形成する工程と、
前記ゲート電極前駆体(47)を酸化して、前記ゲート電極(38,61,71,81)と、シリコン酸化膜またはシリコン酸化窒化膜から成るゲート絶縁膜(37)とを形成する工程とを備え、
前記ゲート電極前駆体(47)を酸化して、前記ゲート電極(38,61,71,81)と前記ゲート絶縁膜(37)とを形成する工程は、
前記ゲート電極前駆体(47)を酸化することによって、前記ゲート電極(38,61,71,81)の端部において他の部分よりも厚く酸化膜を形成して、前記薄膜絶縁膜(46)を厚膜化し、前記ゲート絶縁膜(37)を形成する工程を含み、
前記ゲート絶縁膜(37)は、
前記第1導電型SiCデプレッション領域(36)上の前記ゲート電極(38,61,71,81)の端部の位置における前記ゲート絶縁膜(37)の膜厚が、前記第2導電型SiCボディ領域(33)上における前記ゲート絶縁膜(37)の膜厚の1.84倍以上となり、かつ前記第2導電型SiCボディ領域(33)上における前記ゲート電極(38,61,71,81)の膜厚以下となるように形成されることを特徴とする半導体装置の製造方法。 - SiC半導体基板(31)の一方側の表面上に第1導電型SiCドリフト層(32)を形成する工程と、
前記第1導電型SiCドリフト層(32)の表面部に、第1導電型SiCソース領域(34)を含む第2導電型SiCボディ領域(33)と、前記第1導電型SiCソース領域(34)から離隔して前記第2導電型SiCボディ領域(33)に隣接し、前記第1導電型SiCドリフト層(32)よりドーピング濃度を高められた第1導電型SiCデプレッション領域(36)とを形成する工程と、
前記第2導電型SiCボディ領域(33)および前記第1導電型SiCデプレッション領域(36)の表面部を酸化して、シリコン酸化膜またはシリコン酸化窒化膜から成るゲート絶縁膜(37)を形成する工程と、
前記ゲート絶縁膜(37)上にゲート電極(38,61,71,81)を形成する工程とを備え、
前記第2導電型SiCボディ領域(33)と前記第1導電型SiCデプレッション領域(36)とを形成する工程では、前記第1導電型SiCデプレッション領域(36)の表面部における添加元素の濃度が、前記第2導電型SiCボディ領域(33)の表面部における添加元素の濃度よりも高くなるように、前記第1導電型SiCデプレッション領域(36)を形成し、
前記ゲート絶縁膜(37)は、
前記第1導電型SiCデプレッション領域(36)上の前記ゲート電極(38,61,71,81)の端部の位置における前記ゲート絶縁膜(37)の膜厚が、前記第2導電型SiCボディ領域(33)上における前記ゲート絶縁膜(37)の膜厚の1.84倍以上となり、かつ前記第2導電型SiCボディ領域(33)上における前記ゲート電極(38,61,71,81)の膜厚以下となるように形成されることを特徴とする半導体装置の製造方法。
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WO2014204491A1 (en) * | 2013-06-21 | 2014-12-24 | Microsemi Corporation | Low loss sic mosfet |
US20150236151A1 (en) * | 2014-02-18 | 2015-08-20 | General Electric Company | Silicon carbide semiconductor devices, and methods for manufacturing thereof |
WO2016013182A1 (ja) | 2014-07-24 | 2016-01-28 | パナソニックIpマネジメント株式会社 | 炭化珪素半導体素子およびその製造方法 |
US11222955B2 (en) | 2020-04-22 | 2022-01-11 | Wolfspeed, Inc. | Semiconductor power devices having gate dielectric layers with improved breakdown characteristics and methods of forming such devices |
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JPS57103361A (en) * | 1980-10-29 | 1982-06-26 | Siemens Ag | Mis controlled semiconductor element |
JPS6252470B2 (ja) * | 1978-03-03 | 1987-11-05 | Hitachi Ltd | |
WO2007108439A1 (ja) * | 2006-03-22 | 2007-09-27 | Mitsubishi Electric Corporation | 電力用半導体装置 |
JP2009032919A (ja) * | 2007-07-27 | 2009-02-12 | Sumitomo Electric Ind Ltd | 酸化膜電界効果トランジスタおよびその製造方法 |
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JPH05243274A (ja) * | 1992-03-03 | 1993-09-21 | Nec Corp | 縦型mosfet |
JPH0669507A (ja) * | 1992-05-22 | 1994-03-11 | Nec Corp | パワーmosfet |
JP2002016251A (ja) * | 2000-06-29 | 2002-01-18 | Toshiba Corp | 半導体装置 |
JP3664158B2 (ja) * | 2002-02-19 | 2005-06-22 | 日産自動車株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP3742400B2 (ja) * | 2003-04-23 | 2006-02-01 | 株式会社東芝 | 半導体装置及びその製造方法 |
ITTO20060785A1 (it) * | 2006-11-02 | 2008-05-03 | St Microelectronics Srl | Dispositivo mos resistente alla radiazione ionizzante |
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JPS6252470B2 (ja) * | 1978-03-03 | 1987-11-05 | Hitachi Ltd | |
JPS57103361A (en) * | 1980-10-29 | 1982-06-26 | Siemens Ag | Mis controlled semiconductor element |
WO2007108439A1 (ja) * | 2006-03-22 | 2007-09-27 | Mitsubishi Electric Corporation | 電力用半導体装置 |
JP2009032919A (ja) * | 2007-07-27 | 2009-02-12 | Sumitomo Electric Ind Ltd | 酸化膜電界効果トランジスタおよびその製造方法 |
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