JP5679622B2 - 絶縁膜、およびこれを用いた半導体装置 - Google Patents
絶縁膜、およびこれを用いた半導体装置 Download PDFInfo
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- JP5679622B2 JP5679622B2 JP2008020774A JP2008020774A JP5679622B2 JP 5679622 B2 JP5679622 B2 JP 5679622B2 JP 2008020774 A JP2008020774 A JP 2008020774A JP 2008020774 A JP2008020774 A JP 2008020774A JP 5679622 B2 JP5679622 B2 JP 5679622B2
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- insulating film
- hydrogen
- film
- nitrogen
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
Description
{<N>−<H>}/2≦1.0×1021cm−3
を満たすことを特徴とする。
{<III価金属>−<H>}/2≦1.0×1021cm−3
を満たすことを特徴とする。
{2×<II価金属>−<H>}/2≦1.0×1021cm−3
を満たすことを特徴とする。
{<II価金属>−<H>}/2≦1.0×1021cm−3
を満たすことを特徴とする。
(1)自由に動き回る酸素欠陥がトリガーとなり、アモルファス構造から結晶の析出が簡単に発生し、絶縁膜特性の一様性が保証されなくなる(相分離・結晶化の問題)。
(2)酸素欠陥による欠陥準位がバンドギャップ中に発生して、リーク電流の源となる(酸素欠陥を介したリーク電流の問題)。
(3)酸素欠陥の移動に伴い構造欠陥が発生し、長期信頼性が損なわれる(信頼性の問題)。
(4)酸素欠陥から電子を移すことで、エネルギーが安定化して、大きな閾値電圧(Vth)のシフトが発生する。電極のフェルミ準位が固定化され、p型MISFETの閾値電圧が0.6eV程度大きくなり、ピニングされてしまう問題(p型MISFETにおけるVthのピニング問題)。
本発明の一実施形態による絶縁膜は、主としてIV価金属(Hf,Zr,Ti)或いはIII価金属(La、Y、Sc、Al,ランタン系列Ln、ここでLn=Ce、Pr,Nd,Pm,Sm、Eu,Gd,Tb,Dy,Ho,Er,Tm,Yb,Luである)の酸化物を有する絶縁膜であり、その構成金属よりも低価数の物質、或いは窒素を添加した酸化物絶縁膜である。低価数物質、或いは窒素の添加量に応じた、適量のHを導入する。
{[N]−[H]}/2≦1.1at%
であることが好ましい。より好ましくは、
{[N]−[H]}/2≦0.31at%
である。ここで、{[N]−[H]}/2は、酸素欠陥量と一致する。上記数式は窒素の場合を示したが、他の添加物から考えた場合も、同様の上限が出現する。
{<N>−<H>}/2≦1.0×1021cm−3
であることが好ましい。より好ましくは、
{<N>−<H>}/2≦3.0×1020cm−3
である、と書き直すことも可能である。今後、数式表示を行った時は、特に記述がなくても、表示単位は式の内部で同一とする。
水素と窒素を等量導入することを目指したHfONH膜の第1成膜例を図8(a)、8(b)に示す。素子分離及び、チャネルドーピング(例えばリンPやボロンBを導入)を行なったシリコン基板1上に、HfO2膜をCVD法により成膜し、室温にてプラズマ窒化を行ない、HfON膜2を形成する。その後、プラズマ水素化(室温で60秒)、或いは励起水素による水素化(同様に室温で60秒)を続けて行うことで、原子状に励起された水素を導入し(図8(a))、HfONH膜2が形成される。その後、真空中900℃、60秒の、PDA(Post Deposition Anneal)を行なった。これにより、{[N]−[H]}/2≦1.1at%(或いは、密度表示に直せば、{<N>−<H>}/2≦1.0×1021cm−3)が十分に確保されていた。{[N]−[H]}/2(或いは、{<N>−<H>}/2)は、酸素欠陥量(単位は右辺に記した単位と同一)であり、膜を例えばSTS(scanning tunneling spectroscopy)により測定することにより、膜中に酸素欠陥が残っているか、それとも、水素で埋まっているかを判断することが可能である。このPDAの温度、および処理時間は、十分に水素原子が膜中に拡散出来ることが条件である。
金属酸化物膜の成膜方法としては、上記CVD法以外にも様々な方法が知られている。例えば、蒸着法、スパッタ法、ALD(atomic layer deposition)法などがあるが、どの方法を用いても構わない。絶縁膜を堆積させながら、プラズマ窒素と原子状に励起された水素を膜中に同時に導入する場合は、低温で十分である。HfO2膜の成膜中に、例えば励起水素ガス、アルゴンガス、励起窒素ガスの混合ガスに曝して低温加熱(100℃)すれば、ゲート絶縁膜HfO2に水素と同時に窒素を導入することが出来る。この導入の仕方は、プラズマ窒素と原子状に励起された水素とを、交互に導入しても良い。ここで、NH3ガス、励起酸素、プラズマ水素などを併用しても同様に窒素、水素を導入することが可能である。この場合は、窒素導入後に水素を導入する上記第1成膜例のプロセスと違って、成膜初期段階から、窒素量と水素量を同等レベルに保ちながら、最安定構造を作りながら成膜が出来る点が大きなメリットである。この場合、HfO2膜から酸素を放出させながら行う工程にはならず、初期段階からHfONH膜を作成できる。後から水素化する場合のように酸素を放出させる工程が入ると、絶縁膜上に別の膜を作成する前に水素化をすることが必要となるが、酸素放出の工程が入らなければ、その後の工程が組み易くなる。
次に、金属と酸素からなるイオン性酸化物絶縁膜における、水素Hと窒素Nが両者ともに添加されている場合の適量について説明する。まず、水素量[H]が窒素量[N]より少ないか、ほぼ等しい場合が適当である。ここで、酸素欠陥Voの量は、水素とペアになっていない窒素量の半分であるので{[N]−[H]}/2となる。この量が8.33at%以上になると、酸素欠陥Vo同士が相互作用して、バンドギャップ中に酸素欠陥Voに起因したバンドが出現する。そのため、バンドオフセットΔEcが低下してしまうので、この8.33at%(密度に直すと8.0×1021cm−3)が第一の上限となる。
−1.0at%≦{[N]−[H]}/2≦8.33at%
としている。より好ましくは、
−0.1at%≦{[N]−[H]}/2≦7.4at%
である。ゼロ或いは、ゼロに近い正の値であれば良いのだが、最大でも、7.4at%以下であることが好ましい。これは、7.4at%を超えると、図9に示すように、急激にΔEcの低下が鮮明になってくるためである。これは、酸素欠陥の相互作用によって、ギャップ中に仮想中間状態が発生するためである。
0.0at%≦[N]+[H]≦50.0at%
でなくてはならない。[N]と[H]の合計が50.0at%を超えると、酸素量が極端に低下して、構造を保持できなくなってしまうからである。酸化物として高い誘電率を保つには、酸素の量が母体構造中の酸素量(66.7at%)の半分以上、すなわち、33.3at%以上であることが望ましい。よって、
0.0at%≦[N]+[H]≦33.4at%
であれば、誘電特性の面で望ましい。
16.7at%≦[N]+[H]である。
−1.0at%≦[N]−[H]≦1.0at%
であり、ほぼ分布形状が一致している。なお、精密測定が可能であるならば、
−0.1at%≦[N]−[H]≦0.1at%
であることが望ましい。本実施形態の成膜プロセスを使えば、[N]≧[H]とすることは原理的に可能である。
次に、絶縁膜中における窒素量の上限および下限について説明する。まず、上限について説明する。
6.4×1019cm−3 ≦<III価元素>≦1.6×1022cm−3
であることが好ましく、
3.0×1020cm−3 ≦<III価元素>≦2.0×1021cm−3
であれば、更に好ましいことになる。
この場合は、III価金属元素La、或いはAlの代わりにBaが入りOの代わりにHが入る。Ba量(或いはMg、Ca、Sr)としては、誘電率の低下を招くことを避けるためには、上記のHfO2中のAl量と同等以下の添加量が好ましく、これは酸化物一般に言えることである。つまり、LaAlO3への添加物の添加量に関しては、[添加物量]≦(10.0+10.0)at%(密度に直すと、1.6×1022cm−3)であること、更に好ましくは<添加物量>≦2.0×1021cm−3であることとなる。ここで、LaとAl量を加えた分の半分20at%と、酸化物一般での上限(価電子帯の相互作用が顕著になってくる値)とが密度に換算すると一致していることが分かる。これは、酸化物が壊れる直前の添加量と、価電子帯の相互作用が顕著になる添加量とが同等であることを意味しており、偶然ではない。
6.4×1019cm−3 ≦<II価元素>≦1.6×1022cm−3
であることが好ましく、
3.0×1020cm−3 ≦<II価元素>≦2.0×1021cm−3
であれば、更に好ましいことになる。
6.4×1019cm−3 ≦<II価元素>≦0.8×1022cm−3
であることが好ましく、
3.0×1020cm−3 ≦<II価元素>≦1.0×1021cm−3
であれば、更に好ましいことになる。
本発明の第1実施例によるn型MISFETを図19に示す。この第1実施例のMISFETは、上記一実施形態の酸化膜をゲート絶縁膜として含んでいる。
次に、本発明の第2実施例によるMIM(metal insulator metal)キャパシタを図20に示す。第2実施例によるMIMキャパシタは、基板31上に形成され例えばTiAlNからなるバッファ膜32と、このバッファ膜32上に形成されPtからなる電極33と、電極33上に形成されキャパシタ絶縁膜34と、キャパシタ絶縁膜34上に形成されPtからなる電極35とを備えている。キャパシタ絶縁膜34は、上記実施形態で説明したLaが添加されたHfO2からなっている。
次に、本発明の第3実施例による半導体装置を図21に示す。この第3実施例の半導体装置は、フラッシュメモリのセルトランジスタであって、Si基板41に離間して形成されたソース領域42aおよびドレイン領域42bと、ソース領域42aとドレイン領域42bとの間のチャネル領域43となるSi基板上に形成されたトンネル絶縁膜44と、トンネル絶縁膜44上に形成されたフローティングゲート電極45と、フローティング電極45上に形成された電極間絶縁膜46と、電極間絶縁膜46上に形成された制御ゲート電極47とを備えている。トンネル絶縁膜44は、例えばアモルファスSiONから構成される。電極45、47は、リン(P)がドープされたポリシリコンから形成される。電極間絶縁膜46は、後に詳述するように、上記実施形態による酸化物から形成される。
次に、本発明の第4実施例による半導体装置を図22に示す。本実施例の半導体装置は、図21に示す第3実施例のメモリセルトランジスタのフローティングゲート電極45を、例えばシリコン窒化膜からなる電荷蓄積絶縁膜45Aに置き換えた構成となっており、電荷トラップ型のメモリセルトランジスタである。なお、第3実施例の電極間絶縁膜46は、第4実施例ではブロック絶縁膜46と呼ばれるが、その材質は第3実施例の電極間絶縁膜と同じAl、Hが添加されたHfO2が用いられる。
第1の金属元素と、酸素と、水素と、第2の金属元素または窒素のいずれか一方の元素と前記一方の元素の量を<X>cm −3 、水素量を<H>cm −3 、前記第1の金属元素と前記第2の金属元素の価数差、或いは酸素と窒素の価数差をkと表すとき、
{k×<X>−<H>}/2≦1.0×1021cm−3
の関係を有し、
前記一方の元素が窒素である場合は、窒素の量を<N>cm −3 とすると、<X>=<N>、かつkは酸素と窒素の価数差であって、かつk=1であり、
前記一方の元素が第2の金属元素であり、前記第1の金属元素がIV価金属、第2の金属がIII価金属の場合は、III価金属の量を<III価金属>cm −3 とすると、<X>=<III価金属>、かつk=1であり、
前記一方の元素が第2の金属元素であり、前記第1の金属元素がIV価金属、第2の金属がII価金属の場合は、II価金属の量を<II価金属>cm −3 とすると、<X>=<II価金属>、かつk=2であり、
前記一方の元素が第2の金属元素であり、前記第1の金属元素がIII価金属、第2の金属がII価金属の場合は、<X>=<II価金属>、かつk=1であるように構成してもよい。
{k×<X>−<H>}/2≦3.0×1020cm−3
を満たすように構成してもよい。
6.4×1019cm−3 ≦<X>≦1.6×1022cm−3/k
を満たすように構成してもよい。
3.0×1020cm−3 ≦<X>≦2.0×1021cm−3/k
を満たすように構成してもよい。
前記窒素の量が前記水素の量以上であり、前記水素の原子は、前記第1の金属の1原子を介して前記窒素の原子と結合しているように構成してもよい。
前記III価金属元素の量が前記水素の量以上であり、前記水素に隣接して前記III価金属元素が存在しているように構成してもよい。
前記IV価金属元素がHf,Zr,Tiのグループから選ばれた1つの金属元素を含み、前記III価金属元素がAl,Sc,Y,La,Ce,Pr,Nd,Pm,Sm,Eu,Gd,Tb,Dy,Ho,Er,Tm、Yb,Luのグループから選ばれた1つの金属元素を含むように構成してもよい。
2 HfON膜
11 Si基板
12 ダミーゲート絶縁膜
13 ダミーゲート電極
15 ゲート側壁
16 ソース/ドレイン領域
17 層間絶縁膜
18 ゲート絶縁膜
19 ゲート電極
21 Si基板
22a ソース領域
22b ドレイン領域
23 チャネル領域
24 ゲート絶縁膜
25 ゲート電極
31 Si基板
32 バッファ膜
33 電極
34 キャパシタ絶縁膜
35 電極
41 Si基板
42a ソース領域
42b ドレイン領域
43 チャネル領域
44 トンネル絶縁膜
45 フローティングゲート電極
45A 電荷蓄積膜
46 電極間絶縁膜(ブロック絶縁膜)
47 制御ゲート電極
Claims (8)
- 金属と、水素と、窒素とを含む非晶質の酸化物誘電体膜を有し、前記酸化物誘電体膜内の前記窒素の含有量[N]at%、<N>cm −3 、前記水素の含有量[H]at%、<H>cm −3 、は、
0cm−3≦{<N>−<H>}/2≦3.0×1020cm−3
を満たすとともに、前記酸化物誘電体膜の厚み方向に渡って、
0at%≦[N]−[H]≦1.0at%
を満たす絶縁膜。 - 前記酸化物誘電体膜内の前記窒素の含有量[N]at%および前記水素の含有量[H]at%は、前記酸化物誘電体膜の厚み方向に渡って、
0at%≦[N]−[H]≦0.1at%
を満たす請求項1記載の絶縁膜。 - 前記酸化物誘電体膜内の前記窒素の含有量<N>cm −3 は、
6.4×1019cm−3 ≦<N>≦1.6×1022cm−3
を満たす請求項1または2記載の絶縁膜。 - 前記酸化物誘電体膜内の前記窒素の含有量<N>は、
3.0×1020cm−3 ≦<N>≦2.0×1021cm−3
を満たす請求項1乃至3のいずれかに記載の絶縁膜。 - 半導体基板と、
前記半導体基板に離間して設けられたソース領域およびドレイン領域と、
前記ソース領域と前記ドレイン領域との間のチャネル領域となる前記半導体基板上に設けられた請求項1乃至4のいずれかに記載の絶縁膜と、
前記絶縁膜上に設けられたゲート電極と、
を備えている半導体装置。 - 第1電極と、
前記第1電極上に設けられた請求項1乃至4のいずれかに記載の絶縁膜と、
前記絶縁膜上に設けられた第2電極と、
を備えている半導体装置。 - 半導体基板と、
前記半導体基板に離間して設けられたソース領域およびドレイン領域と、
前記ソース領域と前記ドレイン領域との間のチャネル領域となる前記半導体基板上に設けられた第1絶縁膜と、
前記第1絶縁膜上に設けられた第1電極と、
前記第1電極上に設けられた第2絶縁膜と、
前記第2絶縁膜上に設けられた第2電極と、
を備え、
前記第1絶縁膜および前記第2絶縁膜の少なくとも一方が請求項1乃至4のいずれかに記載の絶縁膜である半導体装置。 - 半導体基板と、
前記半導体基板に離間して設けられたソース領域およびドレイン領域と、
前記ソース領域と前記ドレイン領域との間のチャネル領域となる前記半導体基板上に設けられた第1絶縁膜と、
前記第1絶縁膜上に設けられた電荷蓄積膜と、
前記電荷蓄積膜上に設けられた第2絶縁膜と、
前記第2絶縁膜上に設けられた電極と、
を備え、
前記第1絶縁膜および前記第2絶縁膜の少なくとも一方が請求項1乃至4のいずれかに記載の絶縁膜である半導体装置。
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CN104752231B (zh) | 2015-03-27 | 2016-02-24 | 京东方科技集团股份有限公司 | 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 |
JP6448503B2 (ja) | 2015-09-10 | 2019-01-09 | 東芝メモリ株式会社 | 不揮発性半導体記憶装置 |
CN110024089B (zh) * | 2016-11-30 | 2023-06-27 | 株式会社理光 | 氧化物或氧氮化物绝缘体膜及其形成用涂布液,场效应晶体管及其制造方法 |
CN107742604B (zh) * | 2017-10-19 | 2019-10-29 | 中国科学院电工研究所 | 具有室温铁磁性氢铪共掺杂氧化铟薄膜的制备方法 |
JP7426647B2 (ja) * | 2019-12-13 | 2024-02-02 | 株式会社デンソー | エレクトレット |
KR20210117005A (ko) * | 2020-03-18 | 2021-09-28 | 삼성전자주식회사 | 수소가 함유된 산화물층을 포함하는 반도체 소자 및 커패시터 |
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US6228751B1 (en) * | 1995-09-08 | 2001-05-08 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
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US6642131B2 (en) * | 2001-06-21 | 2003-11-04 | Matsushita Electric Industrial Co., Ltd. | Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film |
JP3937892B2 (ja) | 2002-04-01 | 2007-06-27 | 日本電気株式会社 | 薄膜形成方法および半導体装置の製造方法 |
JP4034202B2 (ja) * | 2003-02-10 | 2008-01-16 | 富士通日立プラズマディスプレイ株式会社 | ガス放電パネル及びその製造方法 |
JP2004336019A (ja) | 2003-04-18 | 2004-11-25 | Advanced Lcd Technologies Development Center Co Ltd | 成膜方法、半導体素子の形成方法、半導体素子、表示装置の形成方法及び表示装置 |
JP4887604B2 (ja) * | 2003-08-29 | 2012-02-29 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4073393B2 (ja) * | 2003-12-02 | 2008-04-09 | 株式会社東芝 | 半導体装置の製造方法 |
JP4919586B2 (ja) | 2004-06-14 | 2012-04-18 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
JP4554446B2 (ja) * | 2005-06-21 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20070049023A1 (en) * | 2005-08-29 | 2007-03-01 | Micron Technology, Inc. | Zirconium-doped gadolinium oxide films |
JP4649357B2 (ja) | 2006-03-30 | 2011-03-09 | 株式会社東芝 | 絶縁膜および半導体装置 |
JP5032145B2 (ja) * | 2006-04-14 | 2012-09-26 | 株式会社東芝 | 半導体装置 |
JP4181195B2 (ja) | 2006-09-14 | 2008-11-12 | 株式会社東芝 | 絶縁膜、およびそれを用いた半導体装置 |
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US20120196431A1 (en) | 2012-08-02 |
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US20090194797A1 (en) | 2009-08-06 |
US9076788B2 (en) | 2015-07-07 |
US20150129948A1 (en) | 2015-05-14 |
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