JP5672055B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 87
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 239000012535 impurity Substances 0.000 claims description 117
- 239000000758 substrate Substances 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 37
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 14
- 229910052796 boron Inorganic materials 0.000 claims description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 239000011574 phosphorus Substances 0.000 claims description 10
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 107
- 229920002120 photoresistant polymer Polymers 0.000 description 67
- 238000005468 ion implantation Methods 0.000 description 51
- 230000001133 acceleration Effects 0.000 description 21
- 239000011229 interlayer Substances 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Claims (8)
- 半導体基板の第1の領域に、第1のゲート絶縁膜を形成する工程と、
前記半導体基板の第2の領域及び第3の領域に、前記第1のゲート絶縁膜よりも薄い第2のゲート絶縁膜を形成する工程と、
前記第1の領域、前記第2の領域及び第3の領域の前記ゲート絶縁膜の上にそれぞれ第1のゲート電極及び第2のゲート電極及び第3のゲート電極を形成する工程と、
前記第1の領域を覆い、且つ前記第2の領域及び前記第3の領域に開口部を有する第1のレジスト膜を形成する工程と、
前記第1のレジスト膜、前記第2のゲート電極及び前記第3のゲート電極をマスクとし、前記半導体基板に第1導電型の第1の不純物をイオン注入して、前記第2のゲート電極及び前記第3のゲート電極の両側にそれぞれポケット領域を形成する工程と、
前記第1のレジスト膜をマスクとし、前記半導体基板に第2導電型の第2の不純物を前記第1の不純物よりも浅くイオン注入して、前記第2のゲート電極及び前記第3のゲート電極の両側にそれぞれ第1のエクステンション領域及び第1の不純物領域を形成する工程と、
前記第1のレジスト膜を除去した後、前記第2の領域を覆い、且つ前記第1の領域及び前記第3の領域に開口部を有する第2のレジスト膜を形成する工程と、
前記第2のレジスト膜、前記第1のゲート電極及び前記第3のゲート電極をマスクとし、前記半導体基板に第2導電型の第3の不純物を前記第1の不純物よりも浅く且つ前記第2の不純物よりも深くイオン注入して、前記第1のゲート電極及び前記第3のゲート電極の両側にそれぞれ第3のエクステンション領域及び第2の不純物領域を形成する工程と、
前記第2のレジスト膜を除去した後、前記半導体基板に第2導電型の第4の不純物を前記第1の不純物よりも深くイオン注入して、前記第1のゲート電極、第2のゲート電極及び第3のゲート電極の両側にそれぞれソース/ドレイン領域を形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 前記第2の不純物の拡散係数は、前記第3の不純物の拡散係数よりも小さいことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1の不純物はホウ素であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2の不純物はヒ素であり、前記第3の不純物はリンであることを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記第1の不純物はヒ素であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2の不純物及び前記第3の不純物はいずれもホウ素であることを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記ポケット領域を形成する工程では、前記半導体基板の法線方向に対して斜め方向から前記半導体基板に前記第1の不純物をイオン注入することを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置の製造方法。
- 前記第2の不純物領域及び前記第3のエクステンション領域を形成する工程では、前記半導体基板の法線方向に対して斜め方向から前記半導体基板に前記第3の不純物をイオン注入することを特徴とする請求項1乃至7のいずれか1項に記載の半導体装置の製造方法。
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JP2011036704A JP5672055B2 (ja) | 2011-02-23 | 2011-02-23 | 半導体装置の製造方法 |
US13/311,866 US8470677B2 (en) | 2011-02-23 | 2011-12-06 | Method of manufacturing semiconductor device |
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JP2000068389A (ja) | 1998-08-25 | 2000-03-03 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP3189819B2 (ja) * | 1999-01-27 | 2001-07-16 | 日本電気株式会社 | 半導体装置の製造方法 |
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WO2004112139A1 (ja) * | 2003-06-10 | 2004-12-23 | Fujitsu Limited | 半導体装置とその製造方法 |
US20070298574A1 (en) * | 2006-06-26 | 2007-12-27 | Texas Instruments Incorporated | Method of fabricating different semiconductor device types with reduced sets of pattern levels |
JP2008288366A (ja) * | 2007-05-17 | 2008-11-27 | Panasonic Corp | 半導体装置及びその製造方法 |
JP5141667B2 (ja) * | 2009-11-13 | 2013-02-13 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
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