JP5665182B2 - 電荷蓄積構造 - Google Patents
電荷蓄積構造 Download PDFInfo
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- JP5665182B2 JP5665182B2 JP2010517382A JP2010517382A JP5665182B2 JP 5665182 B2 JP5665182 B2 JP 5665182B2 JP 2010517382 A JP2010517382 A JP 2010517382A JP 2010517382 A JP2010517382 A JP 2010517382A JP 5665182 B2 JP5665182 B2 JP 5665182B2
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- dielectric layer
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- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- Thin Film Transistor (AREA)
Description
・このプロセスは、接合前、界面上に位置する第1の誘電体層及び第2の誘電体層のうち少なくとも1つの表面上に電気的に活性な欠陥を形成するステップを備え、
・上記欠陥の形成が、制御誘電体層上に優先的に適用されるプラズマ処理によって得られ、プラズマが、酸素、アルゴン、窒素、塩素、又はフッ素を含み、
・本発明の1つの別の実施形態によれば、上記欠陥は、界面上に位置する第1の誘電体層及び第2の誘電体層のうち少なくとも1つの表面上に汚染物質を堆積するのに適切な処理によって得られ、
・この処理は、上記汚染物質を含む環境における熱処理であり、この汚染物質は、有益には、ゲルマニウム原子であり、
・上記処理は、上記汚染物質を含有する溶液のスピンコーティングであり、この汚染物質は、ゲルマニウム、III族元素、IV族元素及びV族元素から選択されたドーパント、K+、Na+、F−及びCl−から選択されたイオン、又は鉄及びアルミニウムから選択された金属であり、
・この接合は、分子付着による接合であり、
・接合前、界面を形成する第1の誘電体層と第2の誘電体層のうち少なくとも1つは、プラズマによって活性化され、
・このプロセスは、接合前、ドナー基板に脆化ゾーンを形成して半導体層を画成するステップと、接合後、脆化ゾーンに沿った剥離を行って半導体層をレシーバ基板に転写するステップとを備え、
・レシーバ基板は、制御誘電体層でコーティングされ、接合前、1017cm−3より高い密度を示すドーパントが、上記制御誘電体層の下にあるレシーバ基板に注入されて、制御誘電体層の下に導電性ドープ層を形成する。
・2つの基板の一方の基板上に、いわゆる、「トンネル」誘電体を形成するステップと、
・他方の基板上に、いわゆる、「制御」誘電体を形成するステップと、
・接合後、トラップ又は電荷リザーバを形成する電気的に活性な欠陥を生じさせるために、2つの誘電体の少なくとも1つの表面を処理するステップと、
・分子付着によって接合するために、トンネル誘電体及び制御誘電体を介して2つの基板を接触させるステップと、
を備える。
トンネル誘電体材料は、以下の材料、すなわち、SiO2、SiO2−xNx(0<x≦1)、二酸化ハフニウムや酸化イットリウム等の高誘電率の誘電体(high k type dielectrics)、ストロンチウム及びチタンの二酸化物(strontium and titanium dioxide)、アルミナ、二酸化ジルコニウム、五酸化タンタル、二酸化チタン、それらの窒化物及びケイ化物から選択される。
期待品質は、論理応用専用のトランジスタのものと同様の厚さのグリッド酸化物の厚さである。層の厚さに直接依存する所望の物理及び電気特性を画成するために使用される、当業者に公知のITRS(「国際半導体技術ロードマップ」)が発行するロードマップが利用可能である。
制御誘電体材料は、以下の材料、すなわち、SiO2、SiO2−xNx(0<x≦1)、二酸化ハフニウムや酸化イットリウム等の高誘電率の誘電体(high k type dielectrics)、ストロンチウム及びチタンの二酸化物(strontium and titanium dioxide)、アルミナ、二酸化ジルコニウム、五酸化タンタル、二酸化チタン、それらの窒化物及びケイ化物から選択される。
概して、電気的に活性な欠陥、例えば、電荷キャリア(電子又は正孔)のトラップと、ある程度まで、電荷キャリアの保持とが可能な原子が生成される。
・誘電体上に溶解状態の汚染物質を堆積するステップと、
・回転により誘電体の表面全体上に汚染物質を分配するステップと、
・過剰な汚染物質をなくすために、回転速度を上げるステップと、
・汚染物質の厚さを確立するために、一定速度で回転するステップと、
・溶媒が蒸発できるように、特定の時間、回転させるステップと、
を備えるとすることができる。
誘電体層は非常に薄いため、表面は接触状態になる前に優先的に活性化される。特に、有益には、プラズマ活性化が使用される。実際、この場合、薄い誘電体が適用可能であり、汚染物質の拡散を防止するために、低い熱処理を維持することが必要である。その結果、欠陥を生じさせるためにプラズマが使用されなくても、接合を促進するために使用されるとすることができる。従って、プラズマ活性化と、上述した汚染技術の任意のものとを組み合わせることが可能である。
基板は、分子付着による接合のために接触状態に配置される。このため、接合前に表面の前処理が実行され、このようにして、満足な基板表面状態を得るために、適切なクリーニング、ブラッシング、及びリンス動作が適用される。
2つの基板の一方(ドナー基板と呼ぶ)が、薄層をもう一方の基板に転写するためにすでに注入されていれば、この転写を可能にする熱処理が適用される。ドナー基板が多孔性ゾーンを備えていれば、機械的な力を適用することで、もう一方の基板に対する剥離及び転写が可能となる。
図3Aを参照すると、ドナー基板10の表面上に、2nm厚さのトンネル誘電体層40が形成され、ドナー基板10に脆化ゾーンを形成するために、層40を介して注入が実行されて、薄層11を画成する。
図4Aを参照すると、薄層11を画成する脆化ゾーンを生じるように、ドナー基板10が注入される。ドナー基板10の表面上に、7nm厚さの制御誘電体層50が形成される。
この代替的な実施形態は、図3A〜図3Eを参照しながら記載され得る。
トランジスタ又は回路は、原則的に、SeOIの薄い半導体層に製造される。コンポーネントのデザインにより、例えば、基板又はBOX下に位置する電極の高極性及びトランジスタのソース及びドレインの接地等、特別に与えられた動作により誘電体に存在するトラップを充放電することが可能となる。
「フラッシュ」タイプのメモリのサイズを縮小するために、二重グリッドメモリが製造される。このように、メモリの有効表面積は、シリコン上の有効表面積を増大させることなく倍増し、集積密度が上がる。二重グリッドモードで動作することにより、グリッドの電流制御も強化される。従って、メモリ効果によりデバイスのしきい値電圧の制御が改良され、より高性能のメモリが得られる。
Claims (6)
- ドナー基板(10)の半導体層(11)と、絶縁体層(60)と、レシーバ基板(20)とを備えるセミコンダクタ・オン・インシュレータタイプの構造において、前記レシーバ基板(20)上に分子付着によって前記ドナー基板(10)を接合するステップを備え、前記ドナー基板(10)及び前記レシーバ基板(20)のうち少なくとも1つが絶縁体層でコーティングされる、セミコンダクタ・オン・インシュレータタイプの構造の製造プロセスであって、電荷キャリアを保持するのに適切な電気的に活性なトラップを備える、いわゆる、トラップ界面(30)を接合界面に形成するステップを備え、
前記トラップ界面を形成する欠陥(31)が、前記構造内の所定の一定の深さに位置し、
前記ドナー基板(10)及び前記レシーバ基板(20)のうち一方が、第1の誘電体層(40)でコーティングされ、前記ドナー基板(10)及び前記レシーバ基板(20)のうち他方が、第2の誘電体層(50)でコーティングされ、前記絶縁体層(60)が、前記第1の誘電体層(40)及び前記第2の誘電体層(50)を接合することによって得られ、前記トラップ界面(30)が、前記第1の誘電体層(40)と前記第2の誘電体層(50)との間の界面で形成され、
前記接合前、前記界面上に位置する前記第1の誘電体層(40)及び前記第2の誘電体層(50)のうち少なくとも1つの表面上に電気的に活性な前記欠陥(31)をプラズマによる処理によって形成するステップを備え、
前記接合前、前記界面を形成する前記第1の誘電体層(40)及び前記第2の誘電体層(50)のうち少なくとも1つが、プラズマによって活性化される、ことを特徴とする、セミコンダクタ・オン・インシュレータタイプの構造の製造プロセス。 - トンネル誘電体層と呼ばれる前記第1の誘電体層(40)の厚さが、1.5〜25nmであり、制御誘電体層と呼ばれる前記第2の誘電体層の厚さが、4〜50nmであることを特徴とする、請求項1に記載のセミコンダクタ・オン・インシュレータタイプの構造の製造プロセス。
- 前記プラズマによる処理が、前記制御誘電体層(50)上に適用されることを特徴とする、請求項2に記載のセミコンダクタ・オン・インシュレータタイプの構造の製造プロセス。
- 前記プラズマが、酸素、アルゴン、窒素、塩素、又はフッ素を含むことを特徴とする、請求項1〜3のいずれか一項に記載のセミコンダクタ・オン・インシュレータタイプの構造の製造プロセス。
- 前記接合前、前記ドナー基板(10)に脆化ゾーンを形成して前記半導体層(11)を画成するステップと、前記接合後、前記脆化ゾーンに沿った剥離を行って前記半導体層(11)を前記レシーバ基板(20)に転写するステップとを備えることを特徴とする、請求項1〜4のいずれか一項に記載のセミコンダクタ・オン・インシュレータタイプの構造の製造プロセス。
- 前記レシーバ基板(20)が、前記制御誘電体層(50)でコーティングされ、前記接合前、1017cm−3より高い密度を示すドーパントが、前記制御誘電体層(50)の下にある前記レシーバ基板(20)に注入されて、前記制御誘電体層(50)の下に導電性ドープ層(24)を形成することを特徴とする、請求項2に記載のセミコンダクタ・オン・インシュレータタイプの構造の製造プロセス。
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FR0756738A FR2919427B1 (fr) | 2007-07-26 | 2007-07-26 | Structure a reservoir de charges. |
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PCT/EP2008/059524 WO2009013268A1 (en) | 2007-07-26 | 2008-07-21 | Charge reservoir structure |
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JP6185474B2 (ja) * | 2012-09-07 | 2017-08-23 | 京セラ株式会社 | 複合基板およびその製造方法 |
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Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09246533A (ja) * | 1996-03-05 | 1997-09-19 | Hitachi Ltd | 半導体装置およびその製造方法 |
FR2748850B1 (fr) * | 1996-05-15 | 1998-07-24 | Commissariat Energie Atomique | Procede de realisation d'un film mince de materiau solide et applications de ce procede |
US5852306A (en) * | 1997-01-29 | 1998-12-22 | Micron Technology, Inc. | Flash memory with nanocrystalline silicon film floating gate |
US6368938B1 (en) * | 1999-10-05 | 2002-04-09 | Silicon Wafer Technologies, Inc. | Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate |
US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
EP1134799A1 (en) * | 2000-03-15 | 2001-09-19 | STMicroelectronics S.r.l. | Reduced thermal process for forming a nanocrystalline silicon layer within a thin oxide layer |
CN1194380C (zh) * | 2000-04-24 | 2005-03-23 | 北京师范大学 | 绝缘体上单晶硅(soi)材料的制造方法 |
WO2002101807A1 (en) * | 2001-06-11 | 2002-12-19 | Rochester Institute Of Technology | Electrostatic interaction systems and methods thereof |
DE10216838A1 (de) * | 2002-04-16 | 2003-11-06 | Infineon Technologies Ag | Feldeffekttransistor, Feldeffekttransistor-Anordnung, Verfahren zum Justieren einer elektrischen Transsistoreigenschaft eines Feldeffektransistors und Verfahren zum Herstellen eines Feldeffekttransistors |
KR100476901B1 (ko) * | 2002-05-22 | 2005-03-17 | 삼성전자주식회사 | 소이 반도체기판의 형성방법 |
US7057234B2 (en) * | 2002-12-06 | 2006-06-06 | Cornell Research Foundation, Inc. | Scalable nano-transistor and memory using back-side trapping |
US6958265B2 (en) * | 2003-09-16 | 2005-10-25 | Freescale Semiconductor, Inc. | Semiconductor device with nanoclusters |
US20070032040A1 (en) * | 2003-09-26 | 2007-02-08 | Dimitri Lederer | Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses |
FR2860341B1 (fr) * | 2003-09-26 | 2005-12-30 | Soitec Silicon On Insulator | Procede de fabrication de structure multicouche a pertes diminuees |
FR2890489B1 (fr) * | 2005-09-08 | 2008-03-07 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant |
JP4661707B2 (ja) * | 2005-10-03 | 2011-03-30 | セイコーエプソン株式会社 | 不揮発性半導体記憶装置および不揮発性半導体記憶装置の製造方法 |
JP2007173354A (ja) * | 2005-12-20 | 2007-07-05 | Shin Etsu Chem Co Ltd | Soi基板およびsoi基板の製造方法 |
JP2007184466A (ja) * | 2006-01-10 | 2007-07-19 | Renesas Technology Corp | 半導体装置およびその製造方法 |
FR2896618B1 (fr) * | 2006-01-23 | 2008-05-23 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat composite |
FR2896619B1 (fr) * | 2006-01-23 | 2008-05-23 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat composite a proprietes electriques ameliorees |
JP5315596B2 (ja) * | 2006-07-24 | 2013-10-16 | 株式会社Sumco | 貼合せsoiウェーハの製造方法 |
US7981754B2 (en) * | 2006-09-07 | 2011-07-19 | Renesas Electronics Corporation | Manufacturing method of bonded SOI substrate and manufacturing method of semiconductor device |
JP4364227B2 (ja) * | 2006-09-29 | 2009-11-11 | 株式会社東芝 | 半導体記憶装置 |
FR2911430B1 (fr) * | 2007-01-15 | 2009-04-17 | Soitec Silicon On Insulator | "procede de fabrication d'un substrat hybride" |
US7955950B2 (en) * | 2007-10-18 | 2011-06-07 | International Business Machines Corporation | Semiconductor-on-insulator substrate with a diffusion barrier |
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CN101681872A (zh) | 2010-03-24 |
US20100187649A1 (en) | 2010-07-29 |
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JP2010534926A (ja) | 2010-11-11 |
KR20100033372A (ko) | 2010-03-29 |
US8802539B2 (en) | 2014-08-12 |
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