JP5544906B2 - 電子装置及びその製造方法 - Google Patents
電子装置及びその製造方法 Download PDFInfo
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- JP5544906B2 JP5544906B2 JP2010022734A JP2010022734A JP5544906B2 JP 5544906 B2 JP5544906 B2 JP 5544906B2 JP 2010022734 A JP2010022734 A JP 2010022734A JP 2010022734 A JP2010022734 A JP 2010022734A JP 5544906 B2 JP5544906 B2 JP 5544906B2
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- Prior art keywords
- heat
- electronic components
- heat sink
- electronic device
- height
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
本発明に係る電子装置10は、図1に示すように、実装高さが異なる複数の電子部品14a、14b、14cが実装されたプリント基板12と、電子部品14a、14b、14cから発生した熱を外界に放熱する放熱板20と、プリント基板12と放熱板20との間に充填したモールド樹脂16とを備えている。そして、放熱板20と複数の電子部品14a、14b、14cとの間には、その複数の電子部品の実装高さの高低差よりも高さが高い熱伝導性バンプ11が圧縮した状態で配列されている。その熱伝導性バンプ11は、複数の電子部品14a、14b、14cと、放熱板2とを熱結合している。
本発明に係る電子装置10の製造方法は、放熱板20の片面に複数の熱伝導性バンプ11を立設する工程と、プリント基板12上に実装された複数の電子部品14a、14b、14cの上面に熱伝導性バンプ11を圧接して、電子部品14a、14b、14cと放熱板20との間で熱伝導性バンプ11を圧縮させる工程と、放熱板20とプリント基板12との間にモールド樹脂16を注入し、そのモールド樹脂16を硬化させる工程と、を含む。
11、11a、11b、11c 熱伝導性バンプ
12、912、932、952 プリント基板
14a、14b、14c、914a、914b、934a、934b、954a、954b、954c 電子部品
16、916 モールド樹脂
20、920、940、960 放熱板
910 半導体装置
911 中間曲板
918 凹凸部
930 半導体モジュール
931a、931b 樹脂部
950 冷却構造体
951 放熱シート
Claims (6)
- 実装高さが異なる複数の電子部品が実装されたプリント基板と、前記電子部品から発生した熱を外界に放熱する放熱板と、前記プリント基板と放熱板との間に充填したモールド樹脂とを備え、
前記放熱板と前記複数の電子部品との間には、前記複数の電子部品の実装高さの高低差よりも高さが高い熱伝導性バンプが圧縮した状態で配列され、
前記熱伝導性バンプが熱伝導性のフィラーとバインダー樹脂とを含み、
当該熱伝導性バンプが前記複数の電子部品と前記放熱板とを熱結合していることを特徴とする電子装置。 - 前記熱伝導性バンプが円錐形状又は角錐形状である、請求項1に記載の電子装置。
- 前記フィラーがCu、Ag、Au、Pd、Ni及びカーボンの群から選ばれる1又は2以上の物質を含有する、請求項1又は2に記載の電子装置。
- 前記バインダー樹脂のガラス転移点が前記モールド樹脂の硬化温度より低い、請求項1又は2に記載の電子装置。
- 前記バインダー樹脂がエポキシ樹脂である、請求項1又は2に記載の電子装置。
- バインダー樹脂中に熱伝導性フィラーを含有させた熱伝導ペーストを印刷工法又はディスペンス工法によって、放熱板の片面に複数の熱伝導性バンプを立設する工程と、
プリント基板上に実装された複数の電子部品の上面に前記熱伝導性バンプを圧接して、前記電子部品と前記放熱板との間で前記熱伝導性バンプを圧縮させる工程と、
前記放熱板と前記プリント基板との間にモールド樹脂を注入し、当該モールド樹脂を硬化させる工程と、を含むことを特徴とする電子装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010022734A JP5544906B2 (ja) | 2010-02-04 | 2010-02-04 | 電子装置及びその製造方法 |
Applications Claiming Priority (1)
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JP2010022734A JP5544906B2 (ja) | 2010-02-04 | 2010-02-04 | 電子装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011159930A JP2011159930A (ja) | 2011-08-18 |
JP5544906B2 true JP5544906B2 (ja) | 2014-07-09 |
Family
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JP2010022734A Expired - Fee Related JP5544906B2 (ja) | 2010-02-04 | 2010-02-04 | 電子装置及びその製造方法 |
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JP (1) | JP5544906B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11177189B2 (en) | 2017-03-31 | 2021-11-16 | Murata Manufacturing Co., Ltd. | Module including heat dissipation structure |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6262552B2 (ja) * | 2014-01-29 | 2018-01-17 | 住友電気工業株式会社 | 電子部品の製造方法 |
CN109935557B (zh) * | 2017-12-19 | 2023-05-30 | 恒劲科技股份有限公司 | 电子封装件及其制法 |
WO2020017582A1 (ja) | 2018-07-20 | 2020-01-23 | 株式会社村田製作所 | モジュール |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5557501A (en) * | 1994-11-18 | 1996-09-17 | Tessera, Inc. | Compliant thermal connectors and assemblies incorporating the same |
JP3679721B2 (ja) * | 2001-03-05 | 2005-08-03 | 富士高分子工業株式会社 | 半導体の冷却構造体 |
JP2004055670A (ja) * | 2002-07-17 | 2004-02-19 | Matsushita Electric Ind Co Ltd | 回路構造体 |
JP2004172489A (ja) * | 2002-11-21 | 2004-06-17 | Nec Semiconductors Kyushu Ltd | 半導体装置およびその製造方法 |
JP2004186294A (ja) * | 2002-12-02 | 2004-07-02 | Denso Corp | 電子装置 |
JP2005251784A (ja) * | 2004-03-01 | 2005-09-15 | Renesas Technology Corp | 半導体モジュールおよびその製造方法 |
-
2010
- 2010-02-04 JP JP2010022734A patent/JP5544906B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11177189B2 (en) | 2017-03-31 | 2021-11-16 | Murata Manufacturing Co., Ltd. | Module including heat dissipation structure |
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JP2011159930A (ja) | 2011-08-18 |
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