JP5528662B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

Info

Publication number
JP5528662B2
JP5528662B2 JP2007241517A JP2007241517A JP5528662B2 JP 5528662 B2 JP5528662 B2 JP 5528662B2 JP 2007241517 A JP2007241517 A JP 2007241517A JP 2007241517 A JP2007241517 A JP 2007241517A JP 5528662 B2 JP5528662 B2 JP 5528662B2
Authority
JP
Japan
Prior art keywords
switch
line
block
voltage
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007241517A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009076501A5 (enExample
JP2009076501A (ja
Inventor
博美 緒方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2007241517A priority Critical patent/JP5528662B2/ja
Application filed by Sony Corp filed Critical Sony Corp
Priority to US12/230,098 priority patent/US7940080B2/en
Priority to TW097134560A priority patent/TWI430398B/zh
Priority to CN201110068579.1A priority patent/CN102157521B/zh
Priority to CN2008101494840A priority patent/CN101393910B/zh
Publication of JP2009076501A publication Critical patent/JP2009076501A/ja
Publication of JP2009076501A5 publication Critical patent/JP2009076501A5/ja
Priority to US12/929,180 priority patent/US8143914B2/en
Priority to US13/371,994 priority patent/US8890568B2/en
Priority to US14/263,598 priority patent/US9058979B2/en
Application granted granted Critical
Publication of JP5528662B2 publication Critical patent/JP5528662B2/ja
Priority to US14/665,662 priority patent/US9252763B2/en
Priority to US14/956,250 priority patent/US9735775B2/en
Priority to US15/664,393 priority patent/US10263617B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2007241517A 2007-09-18 2007-09-18 半導体集積回路 Active JP5528662B2 (ja)

Priority Applications (11)

Application Number Priority Date Filing Date Title
JP2007241517A JP5528662B2 (ja) 2007-09-18 2007-09-18 半導体集積回路
US12/230,098 US7940080B2 (en) 2007-09-18 2008-08-22 Semiconductor integrated circuit
TW097134560A TWI430398B (zh) 2007-09-18 2008-09-09 半導體積體電路
CN201110068579.1A CN102157521B (zh) 2007-09-18 2008-09-18 半导体集成电路
CN2008101494840A CN101393910B (zh) 2007-09-18 2008-09-18 半导体集成电路
US12/929,180 US8143914B2 (en) 2007-09-18 2011-01-06 Semiconductor integrated circuit
US13/371,994 US8890568B2 (en) 2007-09-18 2012-02-13 Semiconductor integrated circuit
US14/263,598 US9058979B2 (en) 2007-09-18 2014-04-28 Semiconductor integrated circuit having a switch, an electrically-conductive electrode line and an electrically-conductive virtual line
US14/665,662 US9252763B2 (en) 2007-09-18 2015-03-23 Semiconductor integrated circuit having a switch, an electrically- conductive electrode line and an electrically-conductive virtual line
US14/956,250 US9735775B2 (en) 2007-09-18 2015-12-01 Semiconductor integrated circuit having a switch, an electrically- conductive electrode line and an electrically-conductive virtual line
US15/664,393 US10263617B2 (en) 2007-09-18 2017-07-31 Semiconductor integrated circuit having a switch, an electrically-conductive electrode line and an electrically-conductive virtual line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007241517A JP5528662B2 (ja) 2007-09-18 2007-09-18 半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013029163A Division JP5549752B2 (ja) 2013-02-18 2013-02-18 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2009076501A JP2009076501A (ja) 2009-04-09
JP2009076501A5 JP2009076501A5 (enExample) 2010-11-18
JP5528662B2 true JP5528662B2 (ja) 2014-06-25

Family

ID=40453812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007241517A Active JP5528662B2 (ja) 2007-09-18 2007-09-18 半導体集積回路

Country Status (4)

Country Link
US (7) US7940080B2 (enExample)
JP (1) JP5528662B2 (enExample)
CN (2) CN102157521B (enExample)
TW (1) TWI430398B (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5528662B2 (ja) * 2007-09-18 2014-06-25 ソニー株式会社 半導体集積回路
US8495547B2 (en) * 2009-11-11 2013-07-23 International Business Machines Corporation Providing secondary power pins in integrated circuit design
JP5404678B2 (ja) * 2011-03-10 2014-02-05 株式会社東芝 電源制御装置
US8451026B2 (en) * 2011-05-13 2013-05-28 Arm Limited Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells
US8902625B2 (en) * 2011-11-22 2014-12-02 Marvell World Trade Ltd. Layouts for memory and logic circuits in a system-on-chip
US8823399B1 (en) 2013-10-07 2014-09-02 Cypress Semiconductor Corporation Detect and differentiate touches from different size conductive objects on a capacitive button
JP6264860B2 (ja) 2013-11-27 2018-01-24 セイコーエプソン株式会社 記録装置
US9305898B2 (en) 2014-01-23 2016-04-05 Freescale Semiconductor, Inc. Semiconductor device with combined power and ground ring structure
US9177834B2 (en) 2014-02-19 2015-11-03 Freescale Semiconductor, Inc. Power bar design for lead frame-based packages
CN109155284B (zh) * 2016-06-01 2022-09-23 株式会社索思未来 半导体集成电路装置
KR102630392B1 (ko) 2016-12-06 2024-01-29 삼성전자주식회사 반도체 장치, 반도체 장치의 레이아웃 설계 방법, 및 반도체 장치의 제조 방법
US10417371B2 (en) * 2017-01-27 2019-09-17 Arm Limited Power grid healing techniques
US10452803B2 (en) * 2017-01-27 2019-10-22 Arm Limited Power grid insertion technique
JP7041368B2 (ja) * 2017-03-29 2022-03-24 株式会社ソシオネクスト 半導体集積回路装置
US10346574B2 (en) * 2017-06-16 2019-07-09 Qualcomm Incorporated Effective substitution of global distributed head switch cells with cluster head switch cells
JP7077816B2 (ja) 2018-06-25 2022-05-31 株式会社ソシオネクスト 半導体装置
WO2020217400A1 (ja) 2019-04-25 2020-10-29 株式会社ソシオネクスト 半導体装置
WO2020217396A1 (ja) 2019-04-25 2020-10-29 株式会社ソシオネクスト 半導体装置
CN112864127B (zh) * 2019-11-28 2024-03-08 扬智科技股份有限公司 集成电路的导线互连结构
CN116472605B (zh) * 2020-11-27 2025-06-24 株式会社索思未来 半导体集成电路装置的设计方法、半导体集成电路装置以及计算机可读记录介质
CN113515826B (zh) * 2021-04-09 2022-11-25 云南电网有限责任公司昆明供电局 配电网合环线路拓扑搜索方法及系统

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2888898B2 (ja) * 1990-02-23 1999-05-10 株式会社日立製作所 半導体集積回路
TW382164B (en) 1996-04-08 2000-02-11 Hitachi Ltd Semiconductor IC device with tunnel current free MOS transistors for power supply intercept of main logic
JP4056107B2 (ja) 1997-06-20 2008-03-05 エルピーダメモリ株式会社 半導体集積回路
JP3847147B2 (ja) 2001-11-22 2006-11-15 富士通株式会社 マルチスレショールド電圧ｍｉｓ集積回路装置及びその回路設計方法
JP3786608B2 (ja) * 2002-01-28 2006-06-14 株式会社ルネサステクノロジ 半導体集積回路装置
JP3951773B2 (ja) 2002-03-28 2007-08-01 富士通株式会社 リーク電流遮断回路を有する半導体集積回路
US7078932B2 (en) * 2003-04-25 2006-07-18 Stmicroelectronics Pvt. Ltd. Programmable logic device with reduced power consumption
US6861753B1 (en) * 2003-10-09 2005-03-01 International Business Machines Corporation Method and apparatus for performing power routing on a voltage island within an integrated circuit chip
JP4435553B2 (ja) * 2003-12-12 2010-03-17 パナソニック株式会社 半導体装置
JP4200926B2 (ja) * 2004-03-10 2008-12-24 ソニー株式会社 半導体集積回路
JP4428514B2 (ja) * 2004-03-30 2010-03-10 株式会社ルネサステクノロジ 半導体集積回路装置
WO2005104233A1 (en) 2004-04-27 2005-11-03 Koninklijke Philips Electronics N.V. Integrated circuit layout for virtual power supply
JP2005327862A (ja) * 2004-05-13 2005-11-24 Toshiba Corp 半導体集積回路及び半導体集積回路の設計方法
US7279926B2 (en) * 2004-05-27 2007-10-09 Qualcomm Incoporated Headswitch and footswitch circuitry for power management
EP1638145A1 (en) * 2004-09-20 2006-03-22 Infineon Technologies AG Embedded switchable power ring
US20090079465A1 (en) * 2005-04-21 2009-03-26 Toshio Sasaki Semiconductor integrated circuit
JP2007158035A (ja) * 2005-12-06 2007-06-21 Seiko Epson Corp 半導体集積回路
US7712066B2 (en) * 2005-12-29 2010-05-04 Agere Systems, Inc. Area-efficient power switching cell
US7509613B2 (en) * 2006-01-13 2009-03-24 Sequence Design, Inc. Design method and architecture for power gate switch placement and interconnection using tapless libraries
JP4188974B2 (ja) 2006-02-06 2008-12-03 株式会社ルネサステクノロジ 半導体集積回路
JP2007243077A (ja) * 2006-03-13 2007-09-20 Renesas Technology Corp 半導体集積回路装置
KR100780750B1 (ko) * 2006-05-11 2007-11-30 한국과학기술원 표준 셀과 파워 게이팅 셀을 이용한 파워 네트워크 및 이를가지는 반도체 장치
US7723867B2 (en) * 2007-05-31 2010-05-25 Arm Limited Power gating of circuits
JP5528662B2 (ja) * 2007-09-18 2014-06-25 ソニー株式会社 半導体集積回路
JP4636077B2 (ja) * 2007-11-07 2011-02-23 ソニー株式会社 半導体集積回路
JP4535134B2 (ja) * 2008-01-16 2010-09-01 ソニー株式会社 半導体集積回路およびその電源制御方法
JP4535136B2 (ja) * 2008-01-17 2010-09-01 ソニー株式会社 半導体集積回路、および、スイッチの配置配線方法

Also Published As

Publication number Publication date
CN102157521A (zh) 2011-08-17
CN102157521B (zh) 2014-08-20
US20120256683A1 (en) 2012-10-11
US10263617B2 (en) 2019-04-16
CN101393910B (zh) 2011-05-18
US8890568B2 (en) 2014-11-18
US9058979B2 (en) 2015-06-16
US20150194955A1 (en) 2015-07-09
JP2009076501A (ja) 2009-04-09
US7940080B2 (en) 2011-05-10
US20170331472A1 (en) 2017-11-16
CN101393910A (zh) 2009-03-25
TW200935559A (en) 2009-08-16
US9252763B2 (en) 2016-02-02
US20160156349A1 (en) 2016-06-02
US8143914B2 (en) 2012-03-27
US9735775B2 (en) 2017-08-15
US20140232448A1 (en) 2014-08-21
US20110102076A1 (en) 2011-05-05
US20090072888A1 (en) 2009-03-19
TWI430398B (zh) 2014-03-11

Similar Documents

Publication Publication Date Title
JP5528662B2 (ja) 半導体集積回路
JP4535136B2 (ja) 半導体集積回路、および、スイッチの配置配線方法
US10748933B2 (en) Semiconductor device
US6900478B2 (en) Multi-threshold MIS integrated circuit device and circuit design method thereof
US20020030510A1 (en) Semiconductor integrated circuit for low power and high speed operation
JP2013030602A (ja) 半導体集積回路装置
JP4492736B2 (ja) 半導体集積回路
JP5486172B2 (ja) 半導体記憶装置
JP5842946B2 (ja) 半導体集積回路
JP5549752B2 (ja) 半導体集積回路
JP5029272B2 (ja) 半導体集積回路
JP2004172627A (ja) 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法
JP4229207B2 (ja) 半導体集積回路
JP5715716B2 (ja) 半導体記憶装置
JP2009135264A (ja) スタンダードセル、スタンダードセルライブラリ、半導体集積回路およびその設計方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100315

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100930

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121130

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121218

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130218

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130917

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140416

R150 Certificate of patent or registration of utility model

Ref document number: 5528662

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250