JP5498687B2 - 薄膜トランジスタの作製方法及び表示装置の作製方法 - Google Patents
薄膜トランジスタの作製方法及び表示装置の作製方法 Download PDFInfo
- Publication number
- JP5498687B2 JP5498687B2 JP2008304588A JP2008304588A JP5498687B2 JP 5498687 B2 JP5498687 B2 JP 5498687B2 JP 2008304588 A JP2008304588 A JP 2008304588A JP 2008304588 A JP2008304588 A JP 2008304588A JP 5498687 B2 JP5498687 B2 JP 5498687B2
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- etching
- film
- electrode layer
- conductive film
- thin film
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Description
本実施の形態では、本発明の薄膜トランジスタの作製方法及び該薄膜トランジスタがマトリクス状に配置された表示装置の作製方法の一例について、図1乃至図25を参照して説明する。
本実施の形態では、本発明の薄膜トランジスタの作製方法及び表示装置の作製方法であって、実施の形態1とは異なるものについて説明する。具体的には、多階調マスクを用いることなく、実施の形態1と同様に薄膜トランジスタを作製する方法について図26乃至図30を参照して説明する。
本実施の形態では、本発明の薄膜トランジスタの作製方法及び表示装置の作製方法であって、実施の形態1及び実施の形態2とは異なるものについて説明する。具体的には、実施の形態1及び実施の形態2にて説明した第1のエッチングにより、第1の導電膜102をエッチングする態様について図31乃至図36を参照して説明する。
本実施の形態は、実施の形態1乃至実施の形態3にて説明した方法により作製した表示パネル又は表示装置を表示部として組み込んだ電子機器について図37乃至図39を参照して説明する。このような電子機器としては、例えば、ビデオカメラ若しくはデジタルカメラ等のカメラ、ヘッドマウントディスプレイ(ゴーグル型ディスプレイ)、カーナビゲーション、プロジェクタ、カーステレオ、パーソナルコンピュータ、携帯情報端末(モバイルコンピュータ、携帯電話または電子書籍等)が挙げられる。それらの一例を図37に示す。
102 第1の導電膜
104 第1の絶縁膜
106 半導体膜
108 不純物半導体膜
110 第2の導電膜
112 第1のレジストマスク
114 薄膜積層体
115 エッチングされた第1の導電膜
116 ゲート電極層
116A ゲート電極層
116B ゲート電極層
116C ゲート電極層
116D ゲート電極層
118 第2のレジストマスク
120 ソース電極及びドレイン電極層
120A ソース電極及びドレイン電極層
120B ソース電極及びドレイン電極層
120C ソース電極及びドレイン電極層
120D ソース電極及びドレイン電極層
122 ソース領域及びドレイン領域
122A ソース領域及びドレイン領域
122B ソース領域及びドレイン領域
122C ソース領域及びドレイン領域
122D ソース領域及びドレイン領域
124 半導体層
126 第1の保護膜
128 第2の保護膜
130 第1の開口部
131 第2の開口部
132 画素電極層
140 グレートーンマスク
141 基板
142 遮光部
143 回折格子部
145 ハーフトーンマスク
146 基板
147 半透光部
148 遮光部
151 角
160A 第3の開口部
160B 第3の開口部
161 第4の開口部
170 第1のレジストマスク
171 第2のレジストマスク
200 携帯電話
201 筐体
202 筐体
203 表示部
204 スピーカ
205 マイクロフォン
206 操作キー
207 ポインティングデバイス
208 表面カメラ用レンズ
209 外部接続端子ジャック
210 イヤホン端子
211 キーボード
212 外部メモリスロット
213 裏面カメラ
214 ライト
221 筐体
222 表示用パネル
223 主画面
224 モデム
225 受信機
226 リモコン操作機
227 表示部
228 サブ画面
229 スピーカ部
231 本体
232 表示部
251 画素部
252 信号線駆動回路
253 走査線駆動回路
254 チューナ
255 映像信号増幅回路
256 映像信号処理回路
257 コントロール回路
258 信号分割回路
259 音声信号増幅回路
260 音声信号処理回路
261 制御回路
262 入力部
263 スピーカ
Claims (8)
- 第1の導電膜、絶縁膜、半導体膜、不純物半導体膜及び第2の導電膜を順に積層して形成し、
前記第2の導電膜上に第1のレジストマスクを形成し、
前記第1のレジストマスクを用いて、前記絶縁膜、前記半導体膜、前記不純物半導体膜及び前記第2の導電膜に第1のエッチングを行って前記第1の導電膜の少なくとも表面を露出させ、
前記第2の導電膜上に第2のレジストマスクを形成し、
前記第1の導電膜の一部にサイドエッチングを伴う第2のエッチングを行ってゲート電極層を形成し、
前記第2のレジストマスクを用いて前記第2の導電膜、前記不純物半導体膜及び前記半導体膜の一部に第3のエッチングを行ってソース電極層及びドレイン電極層、ソース領域層及びドレイン領域層並びに半導体層を形成することを特徴とする薄膜トランジスタの作製方法。 - 第1の導電膜、絶縁膜、半導体膜、不純物半導体膜及び第2の導電膜を順に積層して形成し、
前記第2の導電膜上に凹部を有する第1のレジストマスクを形成し、
前記第1のレジストマスクを用いて、前記絶縁膜、前記半導体膜、前記不純物半導体膜及び前記第2の導電膜に第1のエッチングを行って前記第1の導電膜の少なくとも表面を露出させ、
前記第1のレジストマスクを後退させることで前記第1のレジストマスクの凹部と重畳する前記第2の導電膜を露出させつつ第2のレジストマスクを形成し、
前記第1の導電膜の一部にサイドエッチングを伴う第2のエッチングを行ってゲート電極層を形成し、
前記第2のレジストマスクを用いて前記第2の導電膜、前記不純物半導体膜及び前記半導体膜の一部に第3のエッチングを行ってソース電極層及びドレイン電極層、ソース領域層及びドレイン領域層並びに半導体層を形成することを特徴とする薄膜トランジスタの作製方法。 - 請求項2において、
前記第1のレジストマスクは多階調マスクを用いて形成することを特徴とする薄膜トランジスタの作製方法。 - 請求項1乃至請求項3のいずれか一において、
前記第1のエッチングによって素子領域を形成し、
前記第2のエッチングによって前記素子領域の側面から概ね等しい距離だけ内側に前記ゲート電極層の側面を形成することを特徴とする薄膜トランジスタの作製方法。 - 請求項1乃至請求項4のいずれか一において、
前記第1のエッチングはドライエッチングであり、
前記第2のエッチングはウエットエッチングであることを特徴とする薄膜トランジスタの作製方法。 - 請求項1乃至請求項5のいずれか一に記載の方法により作製した薄膜トランジスタの前記ソース電極層及び前記ドレイン電極層に接続して画素電極を選択的に形成することを特徴とする表示装置の作製方法。
- 請求項1乃至請求項6のいずれか一に記載の方法により薄膜トランジスタを作製し、
前記薄膜トランジスタを覆って保護絶縁膜を形成し、
前記ソース電極層及び前記ドレイン電極層の一部を露出させるように前記保護絶縁膜に開口部を形成し、
前記開口部及び前記保護絶縁膜上に画素電極を選択的に形成することを特徴とする表示装置の作製方法。 - 請求項7において、
前記保護絶縁膜は、CVD法又はスパッタリング法により形成した絶縁膜と、スピンコート法により形成した絶縁膜と、を積層して形成することを特徴とする表示装置の作製方法。
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