JP5498394B2 - トランジスタ及びその形成方法 - Google Patents
トランジスタ及びその形成方法 Download PDFInfo
- Publication number
- JP5498394B2 JP5498394B2 JP2010535978A JP2010535978A JP5498394B2 JP 5498394 B2 JP5498394 B2 JP 5498394B2 JP 2010535978 A JP2010535978 A JP 2010535978A JP 2010535978 A JP2010535978 A JP 2010535978A JP 5498394 B2 JP5498394 B2 JP 5498394B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- dimension
- mobility
- semiconductor material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 41
- 239000000463 material Substances 0.000 claims description 47
- 239000004065 semiconductor Substances 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 11
- 238000001514 detection method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 135
- 239000012212 insulator Substances 0.000 description 17
- 229910052732 germanium Inorganic materials 0.000 description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000004993 emission spectroscopy Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Claims (12)
- 絶縁層(310)の上に、第1のキャリア型の移動度を与える第1の半導体材料の第1の層(305)を形成するステップと、
前記第1の層(305)の上に、前記第1のキャリア型とは逆の第2のキャリア型の移動度を与えるように選択された第2の半導体材料の第2の層(315)を形成するステップと、
前記第2の層(315)内の各構造(330)が、逆T字形状構造のベースを形成する前記第1の層(305)の一部と共に前記逆T字形状構造を形成するように、前記第2の層(315)に少なくとも1つの構造(330)を形成するために、前記第2の層をエッチングするステップと、を有するトランジスタの形成方法。 - 前記第1の層を形成する前記ステップは、電子移動度を上げるように歪ませた第1の半導体材料の前記第1の層を形成するステップを有し、前記第2の層を形成する前記ステップは、ホール移動度を上げるように歪ませた第2の半導体材料の前記第2の層を形成するステップを有する請求項1に記載の方法。
- 前記第1の層を形成する前記ステップは、ホール移動度を上げるように歪ませた第1の半導体材料の前記第1の層を形成するステップを有し、前記第2の層を形成する前記ステップは、電子移動度を上げるように歪ませた第2の半導体材料の前記第2の層を形成するステップを有する請求項1に記載の方法。
- 前記第2の層をエッチングする前記ステップは、前記第2の層と前記第1の層との間の面の平面に平行な第1の寸法および第2の寸法を有する構造を表すパターンを使用して、前記第2の層をエッチングするステップを有し、前記第1の寸法は前記第2の寸法よりも小さく、前記第2の層をエッチングする前記ステップは、前記パターンを介して前記第2の層をエッチングして、前記第1の寸法と、第2の寸法と、前記第1の層と前記第2の層との間の前記面の前記平面に直交する第3の寸法とを有する少なくとも1つの構造を形成するステップを有し、前記第3の寸法は前記第1の寸法よりも大きい請求項1に記載の方法。
- 前記第2の層をエッチングする前記ステップは、前記エッチングプロセスにより前記第1の層がエッチングされないように、エッチング終点の検出技術および所定のエッチング時間の少なくとも1つを使用して停止され、前記方法は、前記第1の層内の各構造が、前記第2の層に形成される対応する構造を有する逆T字形状構造の前記ベースを形成するように、前記第1の層をエッチングして、前記第2の層に形成された少なくとも1つの構造に隣接する少なくとも1つの構造を形成するステップを有する請求項1に記載の方法。
- 埋め込み酸化物層(310)の上に形成され、第1のキャリア型の移動度を与える第1の半導体材料から形成された第1の層(305)と、
前記第1の層(305)に隣接して、前記第1の種類とは逆の前記第2のキャリア型の移動度を与えるように選択された第2の半導体材料から形成された第2の層(315)と、を有し、前記第2の層(315)は、前記第2の層(315)内の各構造(330)が、逆T字形状構造のベースを形成する前記第1の層(305)の一部と共に前記逆T字形状構造を形成するように、前記第2の層(315)をエッチングすることによって、前記第2の層(315)に形成された少なくとも1つの構造(330)を有するトランジスタ(300)。 - 前記第1の層は、電子移動度を上げるように歪ませた第1の半導体材料から形成され、前記第2の層は、ホール移動度を上げるように歪ませた第2の半導体材料から形成されている請求項6に記載のトランジスタ。
- 前記第1の層は、ホール移動度を上げるように歪ませた第1の半導体材料から形成され、前記第2の層は、電子移動度を上げるように歪ませた第2の半導体材料から形成されている請求項6に記載のトランジスタ。
- 前記第2の層に形成された前記少なくとも1つの構造は、前記第2の層と前記第1の層との間の面の平面に平行な第1の寸法および第2の寸法を有する構造のパターンを有し、前記第1の寸法は前記第2の寸法よりも小さく、前記第2の層に形成された前記少なくとも1つの構造は、前記第1の層と前記第2の層との間の前記面の前記平面に直交する第3の寸法を有し、前記第3の寸法は前記第1の寸法よりも大きく、前記トランジスタは、前記第1の層内の各構造が、前記第2の層に形成される対応する構造と共に逆T字形状構造の前記ベースを形成するように、前記第2の層に形成された前記少なくとも1つの構造と隣接する、前記第1の層に形成された少なくとも1つの構造を有する請求項6に記載のトランジスタ。
- 前記トランジスタのソース(415)、ドレイン(420)およびゲート(410)を有し、前記ソース(415)、前記ドレイン(420)および前記ゲート(410)は、前記ゲート(410)の作動時に、前記第1の層および前記第2の層から形成される前記逆T字形状構造が、前記トランジスタの前記ソース(415)と前記ドレイン(420)の間のチャネル領域として機能するように形成されている請求項6に記載のトランジスタ。
- 前記第1の層を形成するステップは、前記第1のキャリア型に前記第1の移動度を与えるように配向した導電面を有する前記第1の層を形成するステップを有し、前記第2の層を形成するステップは、前記第2のキャリア型に前記第2の移動度を与えるように配向した導電面を有する前記第1の層を形成するステップを有する請求項1に記載の方法。
- 前記第1の層は、前記第1のキャリア型に前記第1の移動度を与えるように配向した導電面を有して形成され、前記第2の層は、前記第2のキャリア型に前記第2の移動度を与えるように配向した導電面を有して形成される請求項6に記載のトランジスタ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/948,235 US8288756B2 (en) | 2007-11-30 | 2007-11-30 | Hetero-structured, inverted-T field effect transistor |
US11/948,235 | 2007-11-30 | ||
PCT/US2008/013041 WO2009070252A1 (en) | 2007-11-30 | 2008-11-21 | A hetero-structured, inverted-t field effect transistor |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2011505697A JP2011505697A (ja) | 2011-02-24 |
JP2011505697A5 JP2011505697A5 (ja) | 2011-06-23 |
JP5498394B2 true JP5498394B2 (ja) | 2014-05-21 |
Family
ID=40260725
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010535978A Active JP5498394B2 (ja) | 2007-11-30 | 2008-11-21 | トランジスタ及びその形成方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US8288756B2 (ja) |
EP (1) | EP2220686A1 (ja) |
JP (1) | JP5498394B2 (ja) |
KR (1) | KR101392436B1 (ja) |
CN (1) | CN101884107B (ja) |
TW (1) | TWI450339B (ja) |
WO (1) | WO2009070252A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5285947B2 (ja) * | 2008-04-11 | 2013-09-11 | 株式会社東芝 | 半導体装置、およびその製造方法 |
US8101486B2 (en) * | 2009-10-07 | 2012-01-24 | Globalfoundries Inc. | Methods for forming isolated fin structures on bulk semiconductor material |
US8815677B2 (en) * | 2011-06-14 | 2014-08-26 | Intermolecular, Inc. | Method of processing MIM capacitors to reduce leakage current |
CN102956686A (zh) * | 2011-08-18 | 2013-03-06 | 中国科学院微电子研究所 | 一种硅基锗纳米结构衬底及其制备方法 |
FR2982421A1 (fr) * | 2011-11-09 | 2013-05-10 | Soitec Silicon On Insulator | Finfet a trois grilles sur seoi avec modulation de tension de seuil |
US9583398B2 (en) | 2012-06-29 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having FinFETS with different fin profiles |
US9142400B1 (en) | 2012-07-17 | 2015-09-22 | Stc.Unm | Method of making a heteroepitaxial layer on a seed area |
CN103871885B (zh) * | 2012-12-18 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的制作方法 |
CN104103506B (zh) * | 2013-04-11 | 2018-02-13 | 中国科学院微电子研究所 | 半导体器件制造方法 |
US20170309623A1 (en) * | 2016-04-21 | 2017-10-26 | Globalfoundries Inc. | Method, apparatus, and system for increasing drive current of finfet device |
CN111383917B (zh) * | 2018-12-29 | 2023-02-21 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60210831A (ja) * | 1984-04-04 | 1985-10-23 | Agency Of Ind Science & Technol | 化合物半導体結晶基板の製造方法 |
JPH073814B2 (ja) * | 1984-10-16 | 1995-01-18 | 松下電器産業株式会社 | 半導体基板の製造方法 |
US4994866A (en) * | 1988-01-07 | 1991-02-19 | Fujitsu Limited | Complementary semiconductor device |
US5466949A (en) * | 1994-08-04 | 1995-11-14 | Texas Instruments Incorporated | Silicon oxide germanium resonant tunneling |
US6362071B1 (en) * | 2000-04-05 | 2002-03-26 | Motorola, Inc. | Method for forming a semiconductor device with an opening in a dielectric layer |
US6475890B1 (en) * | 2001-02-12 | 2002-11-05 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology |
US6600170B1 (en) * | 2001-12-17 | 2003-07-29 | Advanced Micro Devices, Inc. | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS |
US6605514B1 (en) * | 2002-07-31 | 2003-08-12 | Advanced Micro Devices, Inc. | Planar finFET patterning using amorphous carbon |
US6800910B2 (en) * | 2002-09-30 | 2004-10-05 | Advanced Micro Devices, Inc. | FinFET device incorporating strained silicon in the channel region |
US6872647B1 (en) * | 2003-05-06 | 2005-03-29 | Advanced Micro Devices, Inc. | Method for forming multiple fins in a semiconductor device |
CN1799146A (zh) * | 2003-05-30 | 2006-07-05 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
US7045401B2 (en) * | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
KR100487566B1 (ko) | 2003-07-23 | 2005-05-03 | 삼성전자주식회사 | 핀 전계 효과 트랜지스터 및 그 형성 방법 |
EP1519420A2 (en) | 2003-09-25 | 2005-03-30 | Interuniversitaire Microelectronica Centrum vzw ( IMEC) | Multiple gate semiconductor device and method for forming same |
JP2005051241A (ja) * | 2003-07-25 | 2005-02-24 | Interuniv Micro Electronica Centrum Vzw | 多層ゲート半導体デバイス及びその製造方法 |
US6855583B1 (en) * | 2003-08-05 | 2005-02-15 | Advanced Micro Devices, Inc. | Method for forming tri-gate FinFET with mesa isolation |
FR2861501B1 (fr) * | 2003-10-22 | 2006-01-13 | Commissariat Energie Atomique | Dispositif microelectronique a effet de champ apte a former un ou plusiseurs canaux de transistors |
US20050116290A1 (en) * | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
US7041576B2 (en) * | 2004-05-28 | 2006-05-09 | Freescale Semiconductor, Inc. | Separately strained N-channel and P-channel transistors |
DE102005045078B4 (de) * | 2004-09-25 | 2009-01-22 | Samsung Electronics Co., Ltd., Suwon | Feldeffekttransistor mit einer verspannten Kanalschicht an Seitenwänden einer Struktur an einem Halbleitersubstrat |
KR100674914B1 (ko) | 2004-09-25 | 2007-01-26 | 삼성전자주식회사 | 변형된 채널층을 갖는 모스 트랜지스터 및 그 제조방법 |
US7393733B2 (en) * | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
ATE549748T1 (de) * | 2005-01-28 | 2012-03-15 | Nxp Bv | Verfahren zur herstellung eines dual-gate fet |
US7470951B2 (en) * | 2005-01-31 | 2008-12-30 | Freescale Semiconductor, Inc. | Hybrid-FET and its application as SRAM |
US20060214233A1 (en) * | 2005-03-22 | 2006-09-28 | Ananthanarayanan Hari P | FinFET semiconductor device |
US20060292719A1 (en) * | 2005-05-17 | 2006-12-28 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US7344962B2 (en) * | 2005-06-21 | 2008-03-18 | International Business Machines Corporation | Method of manufacturing dual orientation wafers |
US7323389B2 (en) * | 2005-07-27 | 2008-01-29 | Freescale Semiconductor, Inc. | Method of forming a FINFET structure |
US7265059B2 (en) * | 2005-09-30 | 2007-09-04 | Freescale Semiconductor, Inc. | Multiple fin formation |
US7396711B2 (en) * | 2005-12-27 | 2008-07-08 | Intel Corporation | Method of fabricating a multi-cornered film |
US7709303B2 (en) * | 2006-01-10 | 2010-05-04 | Freescale Semiconductor, Inc. | Process for forming an electronic device including a fin-type structure |
FR2896620B1 (fr) * | 2006-01-23 | 2008-05-30 | Commissariat Energie Atomique | Circuit integre tridimensionnel de type c-mos et procede de fabrication |
US7544980B2 (en) * | 2006-01-27 | 2009-06-09 | Freescale Semiconductor, Inc. | Split gate memory cell in a FinFET |
JP2007258485A (ja) * | 2006-03-23 | 2007-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
US20070235763A1 (en) * | 2006-03-29 | 2007-10-11 | Doyle Brian S | Substrate band gap engineered multi-gate pMOS devices |
US7803670B2 (en) * | 2006-07-20 | 2010-09-28 | Freescale Semiconductor, Inc. | Twisted dual-substrate orientation (DSO) substrates |
US7799592B2 (en) * | 2006-09-27 | 2010-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tri-gate field-effect transistors formed by aspect ratio trapping |
US7692254B2 (en) * | 2007-07-16 | 2010-04-06 | International Business Machines Corporation | Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure |
-
2007
- 2007-11-30 US US11/948,235 patent/US8288756B2/en active Active
-
2008
- 2008-11-21 KR KR1020107011883A patent/KR101392436B1/ko active IP Right Grant
- 2008-11-21 CN CN2008801156452A patent/CN101884107B/zh active Active
- 2008-11-21 WO PCT/US2008/013041 patent/WO2009070252A1/en active Application Filing
- 2008-11-21 JP JP2010535978A patent/JP5498394B2/ja active Active
- 2008-11-21 EP EP08853153A patent/EP2220686A1/en not_active Ceased
- 2008-11-28 TW TW097146123A patent/TWI450339B/zh active
-
2012
- 2012-08-13 US US13/584,673 patent/US8815658B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20120309141A1 (en) | 2012-12-06 |
US20090140294A1 (en) | 2009-06-04 |
CN101884107B (zh) | 2013-02-13 |
CN101884107A (zh) | 2010-11-10 |
TWI450339B (zh) | 2014-08-21 |
JP2011505697A (ja) | 2011-02-24 |
US8815658B2 (en) | 2014-08-26 |
KR20100098516A (ko) | 2010-09-07 |
US8288756B2 (en) | 2012-10-16 |
EP2220686A1 (en) | 2010-08-25 |
TW200937535A (en) | 2009-09-01 |
WO2009070252A1 (en) | 2009-06-04 |
KR101392436B1 (ko) | 2014-05-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5498394B2 (ja) | トランジスタ及びその形成方法 | |
US6709982B1 (en) | Double spacer FinFET formation | |
US8786057B2 (en) | Integrated circuit on corrugated substrate | |
US7265008B2 (en) | Method of IC production using corrugated substrate | |
US9431512B2 (en) | Methods of forming nanowire devices with spacers and the resulting devices | |
US7247887B2 (en) | Segmented channel MOS transistor | |
KR100748261B1 (ko) | 낮은 누설전류를 갖는 fin 전계효과트랜지스터 및 그제조 방법 | |
US20090001470A1 (en) | Method for forming acute-angle spacer for non-orthogonal finfet and the resulting structure | |
US20150372115A1 (en) | Methods of forming nanowire devices with doped extension regions and the resulting devices | |
US20090289304A1 (en) | Co-integration of multi-gate fet with other fet devices in cmos technology | |
KR100696197B1 (ko) | 실리콘 기판을 이용한 다중 게이트 모스 트랜지스터 및 그제조 방법 | |
US20070259501A1 (en) | Integrating high performance and low power multi-gate devices | |
JP2006522488A (ja) | Finfetデバイス中の構造を形成する方法 | |
TWI614899B (zh) | 增加鰭式場效電晶體及奈米線的開關電流比 | |
JP2007142417A (ja) | コーナ部が支配的なトライ・ゲート型電界効果トランジスタ | |
CN105336772B (zh) | 鳍式tfet及其制造方法 | |
US20070257319A1 (en) | Integrating high performance and low power multi-gate devices | |
KR102133208B1 (ko) | 펀치스루 스토퍼가 배제된 전계효과 트랜지스터 및 이의 제조방법 | |
CN104347508B (zh) | 半导体结构及其形成方法 | |
KR20060027440A (ko) | 용량성 결합된 접합 핀 전계 효과 트랜지스터, 그 제조방법 및 이를 채용하는 상보형 트랜지스터 | |
US10290738B2 (en) | Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device | |
CN104952730A (zh) | 半导体结构及其形成方法 | |
CN113497111A (zh) | 半导体结构及其形成方法 | |
JP2017517895A (ja) | 表面ラフネス散乱を最小化または無くした高性能低電力電界効果トランジスタ素子の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110427 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110427 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130313 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130314 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130607 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130614 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130716 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140219 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140307 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5498394 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |