JP5489454B2 - 積層型半導体パッケージ - Google Patents

積層型半導体パッケージ Download PDF

Info

Publication number
JP5489454B2
JP5489454B2 JP2008331194A JP2008331194A JP5489454B2 JP 5489454 B2 JP5489454 B2 JP 5489454B2 JP 2008331194 A JP2008331194 A JP 2008331194A JP 2008331194 A JP2008331194 A JP 2008331194A JP 5489454 B2 JP5489454 B2 JP 5489454B2
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor package
wiring board
semiconductor
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008331194A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010153651A (ja
JP2010153651A5 (enExample
Inventor
直樹 安田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2008331194A priority Critical patent/JP5489454B2/ja
Publication of JP2010153651A publication Critical patent/JP2010153651A/ja
Publication of JP2010153651A5 publication Critical patent/JP2010153651A5/ja
Application granted granted Critical
Publication of JP5489454B2 publication Critical patent/JP5489454B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2008331194A 2008-12-25 2008-12-25 積層型半導体パッケージ Expired - Fee Related JP5489454B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008331194A JP5489454B2 (ja) 2008-12-25 2008-12-25 積層型半導体パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008331194A JP5489454B2 (ja) 2008-12-25 2008-12-25 積層型半導体パッケージ

Publications (3)

Publication Number Publication Date
JP2010153651A JP2010153651A (ja) 2010-07-08
JP2010153651A5 JP2010153651A5 (enExample) 2012-02-16
JP5489454B2 true JP5489454B2 (ja) 2014-05-14

Family

ID=42572417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008331194A Expired - Fee Related JP5489454B2 (ja) 2008-12-25 2008-12-25 積層型半導体パッケージ

Country Status (1)

Country Link
JP (1) JP5489454B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101930689B1 (ko) 2012-05-25 2018-12-19 삼성전자주식회사 반도체 장치
JP6415365B2 (ja) 2014-03-28 2018-10-31 株式会社ジェイデバイス 半導体パッケージ

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009265A (ja) * 2000-06-21 2002-01-11 Sony Corp 固体撮像装置
JP2003347722A (ja) * 2002-05-23 2003-12-05 Ibiden Co Ltd 多層電子部品搭載用基板及びその製造方法
JP4436179B2 (ja) * 2004-04-20 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体装置
JP2007251070A (ja) * 2006-03-18 2007-09-27 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007281043A (ja) * 2006-04-04 2007-10-25 Matsushita Electric Ind Co Ltd 半導体装置

Also Published As

Publication number Publication date
JP2010153651A (ja) 2010-07-08

Similar Documents

Publication Publication Date Title
JP4205613B2 (ja) 半導体装置
JP4322844B2 (ja) 半導体装置および積層型半導体装置
JP2009239256A (ja) 半導体装置及びその製造方法
US20100140801A1 (en) Device
WO2011086613A1 (ja) 半導体装置及びその製造方法
JP5012612B2 (ja) 半導体デバイスの実装構造体及び実装構造体を用いた電子機器
JP2013239660A (ja) 半導体装置及びその製造方法
JP2009049218A (ja) 半導体装置及び半導体装置の製造方法
JP2006196709A (ja) 半導体装置およびその製造方法
JP2010050150A (ja) 半導体装置及び半導体モジュール
JP5973461B2 (ja) 拡張型半導体チップ及び半導体装置
JP5489454B2 (ja) 積層型半導体パッケージ
JP4494240B2 (ja) 樹脂封止型半導体装置
WO2011021364A1 (ja) 半導体装置およびその製造方法
JP2012009713A (ja) 半導体パッケージおよび半導体パッケージの製造方法
CN100424870C (zh) 半导体模块
JP2010272734A (ja) 半導体装置及びその製造方法
JP4557757B2 (ja) 半導体装置
JP2011061055A (ja) 半導体装置の製造方法
JP2007251226A (ja) 半導体装置
JP2011119619A (ja) 半導体パッケージ
JP4652428B2 (ja) 半導体装置およびその製造方法
JP2009170617A (ja) 半導体装置
JP2005268575A (ja) 半導体装置
KR20250037178A (ko) 회로 기판 및 이를 포함하는 반도체 패키지

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111222

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111222

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20120203

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121018

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121023

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121221

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20130228

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130806

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131007

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140128

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140225

LAPS Cancellation because of no payment of annual fees