JP5489454B2 - 積層型半導体パッケージ - Google Patents
積層型半導体パッケージ Download PDFInfo
- Publication number
- JP5489454B2 JP5489454B2 JP2008331194A JP2008331194A JP5489454B2 JP 5489454 B2 JP5489454 B2 JP 5489454B2 JP 2008331194 A JP2008331194 A JP 2008331194A JP 2008331194 A JP2008331194 A JP 2008331194A JP 5489454 B2 JP5489454 B2 JP 5489454B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor package
- wiring board
- semiconductor
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008331194A JP5489454B2 (ja) | 2008-12-25 | 2008-12-25 | 積層型半導体パッケージ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008331194A JP5489454B2 (ja) | 2008-12-25 | 2008-12-25 | 積層型半導体パッケージ |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010153651A JP2010153651A (ja) | 2010-07-08 |
| JP2010153651A5 JP2010153651A5 (enExample) | 2012-02-16 |
| JP5489454B2 true JP5489454B2 (ja) | 2014-05-14 |
Family
ID=42572417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008331194A Expired - Fee Related JP5489454B2 (ja) | 2008-12-25 | 2008-12-25 | 積層型半導体パッケージ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5489454B2 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101930689B1 (ko) | 2012-05-25 | 2018-12-19 | 삼성전자주식회사 | 반도체 장치 |
| JP6415365B2 (ja) | 2014-03-28 | 2018-10-31 | 株式会社ジェイデバイス | 半導体パッケージ |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002009265A (ja) * | 2000-06-21 | 2002-01-11 | Sony Corp | 固体撮像装置 |
| JP2003347722A (ja) * | 2002-05-23 | 2003-12-05 | Ibiden Co Ltd | 多層電子部品搭載用基板及びその製造方法 |
| JP4436179B2 (ja) * | 2004-04-20 | 2010-03-24 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
| JP2007251070A (ja) * | 2006-03-18 | 2007-09-27 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP2007281043A (ja) * | 2006-04-04 | 2007-10-25 | Matsushita Electric Ind Co Ltd | 半導体装置 |
-
2008
- 2008-12-25 JP JP2008331194A patent/JP5489454B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010153651A (ja) | 2010-07-08 |
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| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
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| A61 | First payment of annual fees (during grant procedure) |
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| LAPS | Cancellation because of no payment of annual fees |