JP5460984B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

Info

Publication number
JP5460984B2
JP5460984B2 JP2008203852A JP2008203852A JP5460984B2 JP 5460984 B2 JP5460984 B2 JP 5460984B2 JP 2008203852 A JP2008203852 A JP 2008203852A JP 2008203852 A JP2008203852 A JP 2008203852A JP 5460984 B2 JP5460984 B2 JP 5460984B2
Authority
JP
Japan
Prior art keywords
semiconductor film
substrate
semiconductor
film
bond substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008203852A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009071287A (ja
JP2009071287A5 (OSRAM
Inventor
舜平 山崎
幸一郎 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2008203852A priority Critical patent/JP5460984B2/ja
Publication of JP2009071287A publication Critical patent/JP2009071287A/ja
Publication of JP2009071287A5 publication Critical patent/JP2009071287A5/ja
Application granted granted Critical
Publication of JP5460984B2 publication Critical patent/JP5460984B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/425—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different crystal properties in different TFTs or within an individual TFT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2008203852A 2007-08-17 2008-08-07 半導体装置の作製方法 Expired - Fee Related JP5460984B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008203852A JP5460984B2 (ja) 2007-08-17 2008-08-07 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007212679 2007-08-17
JP2007212679 2007-08-17
JP2008203852A JP5460984B2 (ja) 2007-08-17 2008-08-07 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2009071287A JP2009071287A (ja) 2009-04-02
JP2009071287A5 JP2009071287A5 (OSRAM) 2011-09-15
JP5460984B2 true JP5460984B2 (ja) 2014-04-02

Family

ID=40363296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008203852A Expired - Fee Related JP5460984B2 (ja) 2007-08-17 2008-08-07 半導体装置の作製方法

Country Status (2)

Country Link
US (2) US7981766B2 (OSRAM)
JP (1) JP5460984B2 (OSRAM)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5498670B2 (ja) * 2007-07-13 2014-05-21 株式会社半導体エネルギー研究所 半導体基板の作製方法
JP5268305B2 (ja) * 2007-08-24 2013-08-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8232598B2 (en) * 2007-09-20 2012-07-31 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5250228B2 (ja) * 2007-09-21 2013-07-31 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI437696B (zh) 2007-09-21 2014-05-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
JP2009094488A (ja) * 2007-09-21 2009-04-30 Semiconductor Energy Lab Co Ltd 半導体膜付き基板の作製方法
JP5452900B2 (ja) * 2007-09-21 2014-03-26 株式会社半導体エネルギー研究所 半導体膜付き基板の作製方法
US9157167B1 (en) 2008-06-05 2015-10-13 Soraa, Inc. High pressure apparatus and method for nitride crystal growth
WO2011044554A1 (en) 2009-10-09 2011-04-14 Soraa, Inc. Method for synthesis of high quality large area bulk gallium based crystals
US20120000415A1 (en) * 2010-06-18 2012-01-05 Soraa, Inc. Large Area Nitride Crystal and Method for Making It
US9543392B1 (en) 2008-12-12 2017-01-10 Soraa, Inc. Transparent group III metal nitride and method of manufacture
US9564320B2 (en) 2010-06-18 2017-02-07 Soraa, Inc. Large area nitride crystal and method for making it
JP2012038932A (ja) * 2010-08-06 2012-02-23 Sumco Corp 半導体ウェーハの薄厚化方法および貼り合せウェーハの製造方法
JP2012150029A (ja) * 2011-01-20 2012-08-09 Yokogawa Electric Corp 振動式トランスデューサおよび振動式トランスデューサの製造方法
JP5417399B2 (ja) * 2011-09-15 2014-02-12 信越化学工業株式会社 複合ウェーハの製造方法
US9543197B2 (en) * 2012-12-19 2017-01-10 Intel Corporation Package with dielectric or anisotropic conductive (ACF) buildup layer
US9433077B2 (en) 2014-02-14 2016-08-30 International Business Machines Corporation Substrate device and electric circuit arrangement having first substrate section perpendicular to second substrate section
DE102014014422A1 (de) * 2014-09-29 2016-03-31 Siltectra Gmbh Kombiniertes Waferherstellungsverfahren mit einer Löcher aufweisenden Aufnahmeschicht
DE102017117873B4 (de) 2016-09-01 2023-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterstruktur und zugehöriges Verfahren
US10438838B2 (en) * 2016-09-01 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and related method
US10940611B2 (en) * 2018-07-26 2021-03-09 Halo Industries, Inc. Incident radiation induced subsurface damage for controlled crack propagation in material cleavage

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590117A (ja) 1991-09-27 1993-04-09 Toshiba Corp 単結晶薄膜半導体装置
JPH07297377A (ja) 1994-04-21 1995-11-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
EP1655633A3 (en) * 1996-08-27 2006-06-21 Seiko Epson Corporation Exfoliating method, transferring method of thin film device, thin film integrated circuit device, and liquid crystal display device
JPH1145862A (ja) * 1997-07-24 1999-02-16 Denso Corp 半導体基板の製造方法
JPH1174208A (ja) * 1997-08-27 1999-03-16 Denso Corp 半導体基板の製造方法
US6540861B2 (en) * 1998-04-01 2003-04-01 Canon Kabushiki Kaisha Member separating apparatus and processing apparatus
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP3432187B2 (ja) 1999-09-22 2003-08-04 シャープ株式会社 半導体装置の製造方法
US20020031909A1 (en) 2000-05-11 2002-03-14 Cyril Cabral Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets
JP4708577B2 (ja) * 2001-01-31 2011-06-22 キヤノン株式会社 薄膜半導体装置の製造方法
FR2823599B1 (fr) * 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
JP4800524B2 (ja) * 2001-09-10 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法、及び、製造装置
US7589032B2 (en) * 2001-09-10 2009-09-15 Semiconductor Energy Laboratory Co., Ltd. Laser apparatus, laser irradiation method, semiconductor manufacturing method, semiconductor device, and electronic equipment
CN100403543C (zh) 2001-12-04 2008-07-16 信越半导体株式会社 贴合晶片及贴合晶片的制造方法
JP2004047691A (ja) * 2002-07-11 2004-02-12 Seiko Epson Corp 半導体装置の製造方法、電気光学装置、及び電子機器
US6818529B2 (en) * 2002-09-12 2004-11-16 Applied Materials, Inc. Apparatus and method for forming a silicon film across the surface of a glass substrate
JP4151420B2 (ja) * 2003-01-23 2008-09-17 セイコーエプソン株式会社 デバイスの製造方法
JP2004311576A (ja) * 2003-04-03 2004-11-04 Toshiba Corp 半導体装置の製造方法
JP3927165B2 (ja) 2003-07-03 2007-06-06 株式会社東芝 半導体装置
US6821826B1 (en) 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
DE102004031708B4 (de) 2004-06-30 2008-02-07 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Substrats mit kristallinen Halbleitergebieten unterschiedlicher Eigenschaften
JP2006040911A (ja) * 2004-07-22 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法
KR100539271B1 (ko) * 2004-07-26 2005-12-27 삼성전자주식회사 휨 방지 재질을 사용하는 반도체 칩의 다이 접착 방법
JP4604594B2 (ja) * 2004-07-30 2011-01-05 株式会社デンソー 半導体基板の製造方法
US7312487B2 (en) 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit
US7298009B2 (en) 2005-02-01 2007-11-20 Infineon Technologies Ag Semiconductor method and device with mixed orientation substrate
JP2007012810A (ja) * 2005-06-29 2007-01-18 Renesas Technology Corp 半導体集積回路装置の製造方法
FR2888402B1 (fr) * 2005-07-06 2007-12-21 Commissariat Energie Atomique Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee
US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator
US7288458B2 (en) * 2005-12-14 2007-10-30 Freescale Semiconductor, Inc. SOI active layer with different surface orientation
US20070283958A1 (en) * 2006-05-23 2007-12-13 Ray Naghavi Positive airway pressure device
JP4380709B2 (ja) * 2007-01-31 2009-12-09 セイコーエプソン株式会社 半導体装置の製造方法
EP1993130A3 (en) 2007-05-17 2011-09-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5268305B2 (ja) 2007-08-24 2013-08-21 株式会社半導体エネルギー研究所 半導体装置の作製方法

Also Published As

Publication number Publication date
US20090047771A1 (en) 2009-02-19
US8445359B2 (en) 2013-05-21
US7981766B2 (en) 2011-07-19
JP2009071287A (ja) 2009-04-02
US20110245958A1 (en) 2011-10-06

Similar Documents

Publication Publication Date Title
JP5460984B2 (ja) 半導体装置の作製方法
JP5205012B2 (ja) 表示装置及び当該表示装置を具備する電子機器
JP5268305B2 (ja) 半導体装置の作製方法
JP5294724B2 (ja) 半導体装置の作製方法
JP5507063B2 (ja) 半導体装置の作製方法
JP5728049B2 (ja) 半導体装置
US8101501B2 (en) Method of manufacturing semiconductor device
JP5250228B2 (ja) 半導体装置の作製方法
JP5255801B2 (ja) 半導体装置の作製方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110803

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110803

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20110803

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130725

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130806

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130920

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131224

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140115

R150 Certificate of patent or registration of utility model

Ref document number: 5460984

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees