JP5390310B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
JP5390310B2
JP5390310B2 JP2009206880A JP2009206880A JP5390310B2 JP 5390310 B2 JP5390310 B2 JP 5390310B2 JP 2009206880 A JP2009206880 A JP 2009206880A JP 2009206880 A JP2009206880 A JP 2009206880A JP 5390310 B2 JP5390310 B2 JP 5390310B2
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JP
Japan
Prior art keywords
data
circuit
data transmission
output
semiconductor integrated
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JP2009206880A
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English (en)
Japanese (ja)
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JP2011059852A5 (enExample
JP2011059852A (ja
Inventor
雅泰 光明
洋一 飯塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009206880A priority Critical patent/JP5390310B2/ja
Priority to US12/876,760 priority patent/US8253436B2/en
Priority to CN201410398881.7A priority patent/CN104252875B/zh
Priority to CN201010279142.8A priority patent/CN102013269B/zh
Publication of JP2011059852A publication Critical patent/JP2011059852A/ja
Publication of JP2011059852A5 publication Critical patent/JP2011059852A5/ja
Priority to US13/470,972 priority patent/US8552758B2/en
Priority to US14/014,104 priority patent/US9208877B2/en
Application granted granted Critical
Publication of JP5390310B2 publication Critical patent/JP5390310B2/ja
Priority to US14/920,313 priority patent/US9673818B2/en
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Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Microcomputers (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2009206880A 2009-09-08 2009-09-08 半導体集積回路 Active JP5390310B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2009206880A JP5390310B2 (ja) 2009-09-08 2009-09-08 半導体集積回路
US12/876,760 US8253436B2 (en) 2009-09-08 2010-09-07 Semiconductor integrated circuit with data transmitting and receiving circuits
CN201010279142.8A CN102013269B (zh) 2009-09-08 2010-09-08 半导体集成电路
CN201410398881.7A CN104252875B (zh) 2009-09-08 2010-09-08 半导体集成电路
US13/470,972 US8552758B2 (en) 2009-09-08 2012-05-14 Semiconductor integrated circuit with data transmitting and receiving circuits
US14/014,104 US9208877B2 (en) 2009-09-08 2013-08-29 Semiconductor integrated circuit with data transmitting and receiving circuits
US14/920,313 US9673818B2 (en) 2009-09-08 2015-10-22 Semiconductor integrated circuit with data transmitting and receiving circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009206880A JP5390310B2 (ja) 2009-09-08 2009-09-08 半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013212463A Division JP5612185B2 (ja) 2013-10-10 2013-10-10 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2011059852A JP2011059852A (ja) 2011-03-24
JP2011059852A5 JP2011059852A5 (enExample) 2012-04-05
JP5390310B2 true JP5390310B2 (ja) 2014-01-15

Family

ID=43647259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009206880A Active JP5390310B2 (ja) 2009-09-08 2009-09-08 半導体集積回路

Country Status (3)

Country Link
US (4) US8253436B2 (enExample)
JP (1) JP5390310B2 (enExample)
CN (2) CN104252875B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5390310B2 (ja) * 2009-09-08 2014-01-15 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5346259B2 (ja) 2009-09-08 2013-11-20 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5363252B2 (ja) 2009-09-09 2013-12-11 ルネサスエレクトロニクス株式会社 半導体集積回路
CN103092809B (zh) * 2011-11-02 2015-09-09 宏达国际电子股份有限公司 电子装置与其处理器内部功能方块的线性区操作方法
US10056124B2 (en) * 2016-12-14 2018-08-21 Realtek Semiconductor Corporation Memory control device for repeating data during a preamble signal or a postamble signal and memory control method
KR102767988B1 (ko) * 2020-05-19 2025-02-14 에스케이하이닉스 주식회사 전자시스템 및 반도체시스템

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JPH0485791A (ja) * 1990-07-27 1992-03-18 Hitachi Ltd 半導体記憶装置
US5467455A (en) * 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
JPH09152923A (ja) 1995-11-29 1997-06-10 Fujitsu Ltd 信号電極の駆動方法、電子装置、および半導体装置
JPH11353228A (ja) 1998-06-10 1999-12-24 Mitsubishi Electric Corp メモリモジュールシステム
JP3425890B2 (ja) * 1999-04-08 2003-07-14 Ｎｅｃエレクトロニクス株式会社 バッファ回路
US6356106B1 (en) 2000-09-12 2002-03-12 Micron Technology, Inc. Active termination in a multidrop memory system
US6380758B1 (en) 2000-09-29 2002-04-30 Intel Corporation Impedance control for wide range loaded signals using distributed methodology
JP2002222921A (ja) 2001-01-25 2002-08-09 Mitsubishi Electric Corp 半導体集積回路
US6904552B2 (en) * 2001-03-15 2005-06-07 Micron Technolgy, Inc. Circuit and method for test and repair
JP3799251B2 (ja) 2001-08-24 2006-07-19 エルピーダメモリ株式会社 メモリデバイス及びメモリシステム
JP3821678B2 (ja) 2001-09-06 2006-09-13 エルピーダメモリ株式会社 メモリ装置
JP3721117B2 (ja) * 2001-10-29 2005-11-30 エルピーダメモリ株式会社 入出力回路と基準電圧生成回路及び半導体集積回路
JP4082519B2 (ja) * 2002-07-22 2008-04-30 株式会社ルネサステクノロジ 半導体集積回路装置、データ処理システム及びメモリシステム
JP2004153690A (ja) 2002-10-31 2004-05-27 Nec Corp トライステートバッファ回路
US7142461B2 (en) 2002-11-20 2006-11-28 Micron Technology, Inc. Active termination control though on module register
CN100565490C (zh) * 2002-11-20 2009-12-02 微米技术有限公司 通过模块上寄存器的主动终止控制
JP2004280926A (ja) * 2003-03-14 2004-10-07 Renesas Technology Corp 半導体記憶装置
KR100626375B1 (ko) 2003-07-21 2006-09-20 삼성전자주식회사 고주파로 동작하는 반도체 메모리 장치 및 모듈
US6901135B2 (en) 2003-08-28 2005-05-31 Bio-Imaging Research, Inc. System for extending the dynamic gain of an X-ray detector
JP4615896B2 (ja) * 2004-05-25 2011-01-19 富士通セミコンダクター株式会社 半導体記憶装置および該半導体記憶装置の制御方法
JP2006040318A (ja) * 2004-07-22 2006-02-09 Canon Inc メモリデバイス制御回路
KR100574989B1 (ko) 2004-11-04 2006-05-02 삼성전자주식회사 데이터 스트로브 버스라인의 효율을 향상시키는메모리장치 및 이를 구비하는 메모리 시스템, 및 데이터스트로브 신호 제어방법
JP2007193431A (ja) * 2006-01-17 2007-08-02 Sharp Corp バス制御装置
JP5125028B2 (ja) * 2006-08-18 2013-01-23 富士通セミコンダクター株式会社 集積回路
JP5019573B2 (ja) 2006-10-18 2012-09-05 キヤノン株式会社 メモリ制御回路とメモリシステム、及びそのメモリ制御方法、及び集積回路
JP5018074B2 (ja) * 2006-12-22 2012-09-05 富士通セミコンダクター株式会社 メモリ装置，メモリコントローラ及びメモリシステム
JP4384207B2 (ja) 2007-06-29 2009-12-16 株式会社東芝 半導体集積回路
KR100884604B1 (ko) * 2007-09-04 2009-02-19 주식회사 하이닉스반도체 충분한 내부 동작 마진을 확보하기 위한 반도체 메모리장치 및 그 방법
JP5191218B2 (ja) * 2007-11-27 2013-05-08 アルパイン株式会社 メモリ制御回路
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JP5731730B2 (ja) * 2008-01-11 2015-06-10 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びその半導体記憶装置を含むデータ処理システム
KR20110001396A (ko) * 2009-06-30 2011-01-06 삼성전자주식회사 전력 소모를 줄일 수 있는 반도체 메모리 장치
JP5390310B2 (ja) * 2009-09-08 2014-01-15 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5346259B2 (ja) 2009-09-08 2013-11-20 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5363252B2 (ja) 2009-09-09 2013-12-11 ルネサスエレクトロニクス株式会社 半導体集積回路
KR101093000B1 (ko) * 2010-05-28 2011-12-12 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 동작 방법
CN102662782B (zh) * 2012-04-17 2014-09-03 华为技术有限公司 一种监控系统总线的方法及装置

Also Published As

Publication number Publication date
US9208877B2 (en) 2015-12-08
CN104252875B (zh) 2019-01-04
CN102013269A (zh) 2011-04-13
CN102013269B (zh) 2014-09-10
JP2011059852A (ja) 2011-03-24
US20110057721A1 (en) 2011-03-10
US9673818B2 (en) 2017-06-06
US20160043721A1 (en) 2016-02-11
CN104252875A (zh) 2014-12-31
US8552758B2 (en) 2013-10-08
US20120223769A1 (en) 2012-09-06
US20130343144A1 (en) 2013-12-26
US8253436B2 (en) 2012-08-28

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