JP5361114B2 - 基板導通を利用した積重ねダイ式の構成をもつ集積回路 - Google Patents
基板導通を利用した積重ねダイ式の構成をもつ集積回路 Download PDFInfo
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- JP5361114B2 JP5361114B2 JP2005358376A JP2005358376A JP5361114B2 JP 5361114 B2 JP5361114 B2 JP 5361114B2 JP 2005358376 A JP2005358376 A JP 2005358376A JP 2005358376 A JP2005358376 A JP 2005358376A JP 5361114 B2 JP5361114 B2 JP 5361114B2
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本発明の一態様によれば集積回路は、積重ね状に配置された複数の集積回路のダイを含み、積重ねの頂部のダイを除く任意のダイが、基板導通を介してそれ自体および積重ねへの追加のダイ少なくとも1つのための電流を担持する。
Claims (7)
- 第1の基板および前記第1の基板の一部分を覆って形成された第1の電源導体を有する第1の集積回路のダイと、
第2の基板および前記第2の基板の一部分を覆って形成された第2の電源導体を有する第2の集積回路のダイとを備え、
前記第2の集積回路のダイが、前記第1の集積回路のダイに積み重ねられかつ少なくとも部分的に重なり合っており、
前記第1の集積回路のダイの前記第1の電源導体が、前記第2の集積回路の前記第2の基板に導通可能に結合され、
前記第2の集積回路に関連する電源電流が、前記第1の集積回路のダイの前記第1の電源導体を介して前記第1の基板、前記第2の基板、並びに前記第1の基板および前記第2の基板間の導電性材料の層を通る基板導通によって担持され、
前記第1および第2の集積回路のダイが、前記それぞれの第1および第2の基板の裏側が互いに向き合う、背中合わせの構成で積み重ねられる、
集積回路。 - 前記第1の集積回路のダイに関連する電源電流が、前記第1の基板を通る基板導通によって担持される請求項1に記載の集積回路。
- 第3の基板および前記第3の基板の一部分を覆って形成された第3の電源導体を有する少なくとも1つの追加の集積回路のダイをさらに備え、前記第3の集積回路のダイが前記第2の集積回路のダイに積み重ねられかつ少なくとも部分的に重なり合っている請求項1に記載の集積回路。
- 前記第1および第2の集積回路のダイが、N個の積み上げられた集積回路のダイのうちの2つであり、ここでNは2より大きく、かつ積重ねの底部のダイを除く各ダイが、下側のダイの電源導体を介して基板導通により電源電流を担持する請求項1に記載の集積回路。
- 前記第2の集積回路のための前記電源電流が、前記第1の集積回路のダイの前記第1の電源導体を介して第2の基板を通る基板導通により担持され、VSS電源電流およびVDD電源電流の1つを含む請求項1に記載の集積回路。
- 積み重ねて配置された複数の集積回路のダイを備え、
前記積重ねの底部のダイを除く前記各ダイが、下側のダイの電源導体および基板を介して、それ自身の基板、並びに該それ自身の基板および該下側のダイの基板間の導電性材料の層を通る基板導通によりその電源電流を担持し、かつ、
前記複数の集積回路のダイの第1および第2の集積回路のダイが、前記第1および第2のダイのそれぞれの第1および第2の基板の裏側が互いに向き合う、背中合わせの構成で積み重ねられる、
集積回路。 - 第1の基板および前記第1の基板の一部分を覆って形成された第1の電源導体を有する第1の集積回路のダイと、
第2の基板および前記第2の基板の一部分を覆って形成された第2の電源導体を有する第2の集積回路のダイとを備え、
前記第2の集積回路のダイが、前記第1の集積回路のダイに積み重ねられかつ少なくとも部分的に重なり合っており、
前記第2の集積回路のための電源電流が、前記第1の集積回路のダイの前記第1の電源導体を介して、前記第1の基板、前記第2の基板、並びに前記第1の基板および前記第2の基板間の導電性材料の層を通る基板導通によって担持され、かつ、
前記第1および第2の集積回路のダイが、前記それぞれの第1および第2の基板の裏側が互いに向き合う、背中合わせの構成で積み重ねられる、
集積回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/010,721 US7400047B2 (en) | 2004-12-13 | 2004-12-13 | Integrated circuit with stacked-die configuration utilizing substrate conduction |
US11/010,721 | 2004-12-13 |
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JP2012207994A Division JP2013033981A (ja) | 2004-12-13 | 2012-09-21 | 基板導通を利用した積重ねダイ式の構成をもつ集積回路 |
Publications (3)
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JP2006173615A JP2006173615A (ja) | 2006-06-29 |
JP2006173615A5 JP2006173615A5 (ja) | 2008-10-02 |
JP5361114B2 true JP5361114B2 (ja) | 2013-12-04 |
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JP2012207994A Pending JP2013033981A (ja) | 2004-12-13 | 2012-09-21 | 基板導通を利用した積重ねダイ式の構成をもつ集積回路 |
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US7623365B2 (en) | 2007-08-29 | 2009-11-24 | Micron Technology, Inc. | Memory device interface methods, apparatus, and systems |
US8106520B2 (en) | 2008-09-11 | 2012-01-31 | Micron Technology, Inc. | Signal delivery in stacked device |
US8063491B2 (en) * | 2008-09-30 | 2011-11-22 | Micron Technology, Inc. | Stacked device conductive path connectivity |
CN202758883U (zh) | 2009-05-26 | 2013-02-27 | 拉姆伯斯公司 | 堆叠的半导体器件组件 |
KR102526614B1 (ko) * | 2017-10-31 | 2023-04-27 | 엘지디스플레이 주식회사 | 게이트 드라이버와 이를 포함한 전계 발광 표시장치 |
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-
2004
- 2004-12-13 US US11/010,721 patent/US7400047B2/en not_active Expired - Fee Related
-
2005
- 2005-12-13 JP JP2005358376A patent/JP5361114B2/ja not_active Expired - Fee Related
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US20060125069A1 (en) | 2006-06-15 |
US7400047B2 (en) | 2008-07-15 |
JP2006173615A (ja) | 2006-06-29 |
JP2013033981A (ja) | 2013-02-14 |
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