JP5284564B2 - 垂直方向に配列されたナノロッドおよびその配列への電気接点をつくるためのシステムおよび方法 - Google Patents
垂直方向に配列されたナノロッドおよびその配列への電気接点をつくるためのシステムおよび方法 Download PDFInfo
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- JP5284564B2 JP5284564B2 JP2005361927A JP2005361927A JP5284564B2 JP 5284564 B2 JP5284564 B2 JP 5284564B2 JP 2005361927 A JP2005361927 A JP 2005361927A JP 2005361927 A JP2005361927 A JP 2005361927A JP 5284564 B2 JP5284564 B2 JP 5284564B2
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Description
本発明は、配列内の各ナノロッドが基板の表面と平行でない方向に伸びているナノロッドの配列を基板の表面に形成するステップと、前記配列の少なくとも一部を包囲するために第1の防食層を堆積するステップと、前記第1の防食層を堆積して前記配列の少なくとも一部を包囲するステップと、前記第1の防食層の上部の厚さを除去し複数のナノロッドの上部を露出するステップと、前記複数のナノロッドの上部と電気的に接触している第1の接点層を第1の防食層上に形成するステップと、を含むナノロッド装置の製造方法である。
また、前記製造方法において、前記防食層の厚さを除去する前に前記第1の防食層をマスクするステップを含むことが好ましい。
また、前記製造方法において、前記第1の接点層をマスキングするステップと、所定のパターンにしたがって前記第1の接点層をエッチングするステップと、を含むことが好ましい。
また、前記製造方法において、前記基板は成長基板であり、前記方法は、前記第1の接点層上にハンドルウエハを結合するステップと、前記成長基板を除去するステップと、前記第1の防食層の底部の厚さを除去して複数のナノロッドの底部を露出するステップと、前記複数のナノロッドの露出された底部を金属化するステップと、を含むことが好ましい。
また、前記製造方法において、前記ハンドルウエハの少なくとも一部を除去して複数のナノロッドの1つのナノロッドを複数のナノロッドの他のナノロッドから分離することを可能にし金属化された両端を有するフリースタンディングナノロッドにするステップを含むことが好ましい。
また、前記製造方法において、前記基板は、前記ナノロッドと電気的接触をする第1の電極であり、前記第1の接点層は、第2の電極であり、前記方法は、前記基板の少なくとも一部を除去して複数のナノロッドの1つのナノロッドを複数のナノロッドの他のナノロッドから分離することを可能にしフリースタンディングナノロッドにするステップを含むことが好ましい。
また、前記製造方法において、第1の接点層の上部の厚さを除去して複数のナノロッドの上部の一部を露出するステップと、前記第2の防食層を堆積して上部の部分を包囲するステップと、前記第2の防食層の上部の厚さを除去して上部の部分の一部を露出するステップと、上部の部分と電気的に接触している第2の防食層上に第2の接点層を形成するステップと、を含むことが好ましい。
また、前記製造方法において、前記基板は、前記ナノロッドと電気的接触をする第1の電極であり、前記第1の接点層は、第2の電極であり、前記第2の接点層は、第3の電極であり、前記方法は、前記基板の少なくとも一部を除去して複数のナノロッドの1つのナノロッドを複数のナノロッドの他のナノロッドから分離することを可能にしフリースタンディングナノロッドにするステップを含むことが好ましい。
Claims (2)
- 配列内の各ナノロッドが基板の表面と平行でない方向に伸びているナノロッドの配列を基板の表面に形成するステップと、
第1の防食層を堆積して前記配列の少なくとも一部を包囲するステップと、
前記第1の防食層の上部の厚さを除去し複数のナノロッドの上部を露出するステップと、
前記複数のナノロッドの上部と電気的に接触している第1の接点層を第1の防食層上に形成するステップと、
前記第1の防食層の厚さを除去する前に前記第1の防食層をマスクするステップと、
を含み、
前記基板は成長基板であり、
さらに、
前記第1の接点層上にハンドルウエハを結合するステップと、
前記成長基板を除去するステップと、
前記第1の防食層の底部の厚さを除去して複数のナノロッドの底部を露出するステップと、
前記複数のナノロッドの露出された底部を金属化するステップと、
を含むナノロッド装置の製造方法。 - 前記第1の接点層をマスキングするステップと、
所定のパターンにしたがって前記第1の接点層をエッチングするステップと、
を含む請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/015,665 US7202173B2 (en) | 2004-12-20 | 2004-12-20 | Systems and methods for electrical contacts to arrays of vertically aligned nanorods |
US11/015,665 | 2004-12-20 |
Publications (3)
Publication Number | Publication Date |
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JP2006187857A JP2006187857A (ja) | 2006-07-20 |
JP2006187857A5 JP2006187857A5 (ja) | 2009-02-05 |
JP5284564B2 true JP5284564B2 (ja) | 2013-09-11 |
Family
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JP2005361927A Expired - Fee Related JP5284564B2 (ja) | 2004-12-20 | 2005-12-15 | 垂直方向に配列されたナノロッドおよびその配列への電気接点をつくるためのシステムおよび方法 |
Country Status (2)
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US (1) | US7202173B2 (ja) |
JP (1) | JP5284564B2 (ja) |
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