JP5259954B2 - 基板上に歪層を製造する方法と層構造 - Google Patents
基板上に歪層を製造する方法と層構造 Download PDFInfo
- Publication number
- JP5259954B2 JP5259954B2 JP2006504293A JP2006504293A JP5259954B2 JP 5259954 B2 JP5259954 B2 JP 5259954B2 JP 2006504293 A JP2006504293 A JP 2006504293A JP 2006504293 A JP2006504293 A JP 2006504293A JP 5259954 B2 JP5259954 B2 JP 5259954B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- strained
- silicon
- substrate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3204—Materials thereof being Group IVA semiconducting materials
- H10P14/3211—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/938—Lattice strain control or utilization
Landscapes
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10318283.7 | 2003-04-22 | ||
| DE10318283A DE10318283A1 (de) | 2003-04-22 | 2003-04-22 | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
| PCT/DE2004/000736 WO2004095552A2 (de) | 2003-04-22 | 2004-04-08 | Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006524426A JP2006524426A (ja) | 2006-10-26 |
| JP2006524426A5 JP2006524426A5 (https=) | 2012-10-04 |
| JP5259954B2 true JP5259954B2 (ja) | 2013-08-07 |
Family
ID=33304879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006504293A Expired - Lifetime JP5259954B2 (ja) | 2003-04-22 | 2004-04-08 | 基板上に歪層を製造する方法と層構造 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7615471B2 (https=) |
| EP (1) | EP1616345A2 (https=) |
| JP (1) | JP5259954B2 (https=) |
| DE (1) | DE10318283A1 (https=) |
| WO (1) | WO2004095552A2 (https=) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10318284A1 (de) * | 2003-04-22 | 2004-11-25 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
| US7202145B2 (en) * | 2004-06-03 | 2007-04-10 | Taiwan Semiconductor Manufacturing Company | Strained Si formed by anneal |
| DE102004048096A1 (de) * | 2004-09-30 | 2006-04-27 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
| US7202124B2 (en) * | 2004-10-01 | 2007-04-10 | Massachusetts Institute Of Technology | Strained gettering layers for semiconductor processes |
| JP4654710B2 (ja) * | 2005-02-24 | 2011-03-23 | 信越半導体株式会社 | 半導体ウェーハの製造方法 |
| US8105908B2 (en) * | 2005-06-23 | 2012-01-31 | Applied Materials, Inc. | Methods for forming a transistor and modulating channel stress |
| KR100673020B1 (ko) | 2005-12-20 | 2007-01-24 | 삼성전자주식회사 | 전계효과 소오스/드레인 영역을 가지는 반도체 장치 |
| US7339230B2 (en) * | 2006-01-09 | 2008-03-04 | International Business Machines Corporation | Structure and method for making high density mosfet circuits with different height contact lines |
| DE102006004870A1 (de) | 2006-02-02 | 2007-08-16 | Siltronic Ag | Halbleiterschichtstruktur und Verfahren zur Herstellung einer Halbleiterschichtstruktur |
| DE102006010273B4 (de) * | 2006-03-02 | 2010-04-15 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte, Schichtstapel und dessen Verwendung |
| US7494886B2 (en) | 2007-01-12 | 2009-02-24 | International Business Machines Corporation | Uniaxial strain relaxation of biaxial-strained thin films using ion implantation |
| US8471307B2 (en) * | 2008-06-13 | 2013-06-25 | Texas Instruments Incorporated | In-situ carbon doped e-SiGeCB stack for MOS transistor |
| DE102008035816B4 (de) | 2008-07-31 | 2011-08-25 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG, 01109 | Leistungssteigerung in PMOS- und NMOS-Transistoren durch Verwendung eines eingebetteten verformten Halbleitermaterials |
| TWI430338B (zh) * | 2008-10-30 | 2014-03-11 | 康寧公司 | 使用定向剝離作用製造絕緣體上半導體結構之方法及裝置 |
| US8003491B2 (en) * | 2008-10-30 | 2011-08-23 | Corning Incorporated | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
| US9059201B2 (en) * | 2010-04-28 | 2015-06-16 | Acorn Technologies, Inc. | Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation |
| US8361889B2 (en) * | 2010-07-06 | 2013-01-29 | International Business Machines Corporation | Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator |
| US8822306B2 (en) * | 2010-09-30 | 2014-09-02 | Infineon Technologies Ag | Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core |
| US8404562B2 (en) | 2010-09-30 | 2013-03-26 | Infineon Technologies Ag | Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core |
| DE102010064290B3 (de) * | 2010-12-28 | 2012-04-19 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verformungserhöhung in Transistoren mit einem eingebetteten verformungsinduzierenden Halbleitermaterial durch Kondensation der legierungsbildenden Substanz |
| US8859348B2 (en) * | 2012-07-09 | 2014-10-14 | International Business Machines Corporation | Strained silicon and strained silicon germanium on insulator |
| EP2741320B1 (en) * | 2012-12-05 | 2020-06-17 | IMEC vzw | Manufacturing method of a finfet device with dual-strained channels |
| FR3003686B1 (fr) * | 2013-03-20 | 2016-11-04 | St Microelectronics Crolles 2 Sas | Procede de formation d'une couche de silicium contraint |
| US9269714B2 (en) * | 2013-06-10 | 2016-02-23 | Globalfoundries Inc. | Device including a transistor having a stressed channel region and method for the formation thereof |
| FR3041146B1 (fr) * | 2015-09-11 | 2018-03-09 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de mise en tension d'un film semi-conducteur |
| US9871057B2 (en) * | 2016-03-03 | 2018-01-16 | Globalfoundries Inc. | Field-effect transistors with a non-relaxed strained channel |
| FR3050569B1 (fr) * | 2016-04-26 | 2018-04-13 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Fabrication amelioree de silicium contraint en tension sur isolant par amorphisation puis recristallisation |
| WO2018004527A1 (en) * | 2016-06-28 | 2018-01-04 | Intel Corporation | Cell for n-negative differential resistance (ndr) latch |
| US9818875B1 (en) * | 2016-10-17 | 2017-11-14 | International Business Machines Corporation | Approach to minimization of strain loss in strained fin field effect transistors |
| CN111785679A (zh) * | 2020-07-29 | 2020-10-16 | 联合微电子中心有限责任公司 | 半导体器件及其制备方法 |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3627647A (en) * | 1969-05-19 | 1971-12-14 | Cogar Corp | Fabrication method for semiconductor devices |
| US5442205A (en) * | 1991-04-24 | 1995-08-15 | At&T Corp. | Semiconductor heterostructure devices with strained semiconductor layers |
| US5344785A (en) * | 1992-03-13 | 1994-09-06 | United Technologies Corporation | Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate |
| US5847419A (en) * | 1996-09-17 | 1998-12-08 | Kabushiki Kaisha Toshiba | Si-SiGe semiconductor device and method of fabricating the same |
| JP3645390B2 (ja) * | 1997-01-17 | 2005-05-11 | 株式会社東芝 | 半導体装置およびその製造方法 |
| DE19802977A1 (de) * | 1998-01-27 | 1999-07-29 | Forschungszentrum Juelich Gmbh | Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement |
| JP3884203B2 (ja) * | 1998-12-24 | 2007-02-21 | 株式会社東芝 | 半導体装置の製造方法 |
| JP4212228B2 (ja) * | 1999-09-09 | 2009-01-21 | 株式会社東芝 | 半導体装置の製造方法 |
| US6326667B1 (en) * | 1999-09-09 | 2001-12-04 | Kabushiki Kaisha Toshiba | Semiconductor devices and methods for producing semiconductor devices |
| US6690043B1 (en) * | 1999-11-26 | 2004-02-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| JP4226175B2 (ja) * | 1999-12-10 | 2009-02-18 | 富士通株式会社 | 半導体装置およびその製造方法 |
| US6429061B1 (en) * | 2000-07-26 | 2002-08-06 | International Business Machines Corporation | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation |
| JP2004531054A (ja) | 2001-03-02 | 2004-10-07 | アンバーウェーブ システムズ コーポレイション | 高速cmos電子機器及び高速アナログ回路のための緩和シリコンゲルマニウムプラットフォーム |
| JP3933405B2 (ja) * | 2001-03-06 | 2007-06-20 | シャープ株式会社 | 半導体基板、半導体装置及びそれらの製造方法 |
| JP3875040B2 (ja) * | 2001-05-17 | 2007-01-31 | シャープ株式会社 | 半導体基板及びその製造方法ならびに半導体装置及びその製造方法 |
| US6593625B2 (en) | 2001-06-12 | 2003-07-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
| US20030077882A1 (en) * | 2001-07-26 | 2003-04-24 | Taiwan Semiconductor Manfacturing Company | Method of forming strained-silicon wafer for mobility-enhanced MOSFET device |
| US6515335B1 (en) * | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
| US6746902B2 (en) * | 2002-01-31 | 2004-06-08 | Sharp Laboratories Of America, Inc. | Method to form relaxed sige layer with high ge content |
| DE10218381A1 (de) * | 2002-04-24 | 2004-02-26 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer oder mehrerer einkristalliner Schichten mit jeweils unterschiedlicher Gitterstruktur in einer Ebene einer Schichtenfolge |
| US6972245B2 (en) * | 2002-05-15 | 2005-12-06 | The Regents Of The University Of California | Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures |
| US6689671B1 (en) * | 2002-05-22 | 2004-02-10 | Advanced Micro Devices, Inc. | Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate |
| US6774015B1 (en) * | 2002-12-19 | 2004-08-10 | International Business Machines Corporation | Strained silicon-on-insulator (SSOI) and method to form the same |
| DE10310740A1 (de) * | 2003-03-10 | 2004-09-30 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen |
| US6767802B1 (en) * | 2003-09-19 | 2004-07-27 | Sharp Laboratories Of America, Inc. | Methods of making relaxed silicon-germanium on insulator via layer transfer |
-
2003
- 2003-04-22 DE DE10318283A patent/DE10318283A1/de not_active Withdrawn
-
2004
- 2004-04-08 WO PCT/DE2004/000736 patent/WO2004095552A2/de not_active Ceased
- 2004-04-08 EP EP04726422A patent/EP1616345A2/de not_active Withdrawn
- 2004-04-08 US US10/554,074 patent/US7615471B2/en not_active Expired - Fee Related
- 2004-04-08 JP JP2006504293A patent/JP5259954B2/ja not_active Expired - Lifetime
-
2009
- 2009-07-02 US US12/496,676 patent/US7915148B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20090298301A1 (en) | 2009-12-03 |
| US20060220127A1 (en) | 2006-10-05 |
| DE10318283A1 (de) | 2004-11-25 |
| WO2004095552A2 (de) | 2004-11-04 |
| JP2006524426A (ja) | 2006-10-26 |
| US7915148B2 (en) | 2011-03-29 |
| US7615471B2 (en) | 2009-11-10 |
| WO2004095552A3 (de) | 2004-12-02 |
| EP1616345A2 (de) | 2006-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5259954B2 (ja) | 基板上に歪層を製造する方法と層構造 | |
| JP2006524426A5 (https=) | ||
| US7390725B2 (en) | Strained silicon on insulator from film transfer and relaxation by hydrogen implantation | |
| JP4716733B2 (ja) | 歪みシリコン・オン・インシュレータ(ssoi)を形成する方法 | |
| KR100521708B1 (ko) | 반도체 기판을 제조하는 방법 | |
| US6573126B2 (en) | Process for producing semiconductor article using graded epitaxial growth | |
| JP3970011B2 (ja) | 半導体装置及びその製造方法 | |
| JP5065676B2 (ja) | 基板上に歪層を製造する方法及び層構造 | |
| US6940089B2 (en) | Semiconductor device structure | |
| US6723541B2 (en) | Method of producing semiconductor device and semiconductor substrate | |
| US7825470B2 (en) | Transistor and in-situ fabrication process | |
| US7897480B2 (en) | Preparation of high quality strained-semiconductor directly-on-insulator substrates | |
| CN100405534C (zh) | 半导体结构的制造方法 | |
| JP2004014856A (ja) | 半導体基板の製造方法及び半導体装置の製造方法 | |
| JP2008505482A (ja) | シリコン・ゲルマニウム・バッファで絶縁体上に歪みSi/SiGeを形成する方法 | |
| Mazuré et al. | Advanced SOI Substrate Manufacturing | |
| CN1799136A (zh) | 通过在硅锗合金熔点附近进行退火而制造sgoi的方法 | |
| CN101142669B (zh) | SiGe结构的形成和处理 | |
| JP4853990B2 (ja) | 絶縁体上に歪み結晶層を製造する方法、前記方法による半導体構造及び製造された半導体構造 | |
| JP2008515209A (ja) | 基体の上に歪み層を製造する方法、及び層構造 | |
| Ghyselen et al. | Strained Silicon on Insulator wafers made by the Smart Cut™ technology | |
| JP2004356644A (ja) | 半導体基板の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070216 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20100518 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110308 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110525 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110601 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110707 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110714 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110805 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110812 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110906 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120327 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120626 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120703 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120725 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120801 |
|
| A524 | Written submission of copy of amendment under article 19 pct |
Free format text: JAPANESE INTERMEDIATE CODE: A524 Effective date: 20120820 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120821 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121218 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130301 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130416 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130425 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160502 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| S801 | Written request for registration of abandonment of right |
Free format text: JAPANESE INTERMEDIATE CODE: R311801 |
|
| ABAN | Cancellation due to abandonment | ||
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |