JP5259343B2 - メモリ装置 - Google Patents
メモリ装置 Download PDFInfo
- Publication number
- JP5259343B2 JP5259343B2 JP2008281316A JP2008281316A JP5259343B2 JP 5259343 B2 JP5259343 B2 JP 5259343B2 JP 2008281316 A JP2008281316 A JP 2008281316A JP 2008281316 A JP2008281316 A JP 2008281316A JP 5259343 B2 JP5259343 B2 JP 5259343B2
- Authority
- JP
- Japan
- Prior art keywords
- error
- equation
- calculation
- syndrome
- finite field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1575—Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
- H03M13/3715—Adaptation to the number of estimated errors or to the channel state
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Pure & Applied Mathematics (AREA)
- Algebra (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Error Detection And Correction (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008281316A JP5259343B2 (ja) | 2008-10-31 | 2008-10-31 | メモリ装置 |
| US12/555,507 US7962838B2 (en) | 2008-10-31 | 2009-09-08 | Memory device with an ECC system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008281316A JP5259343B2 (ja) | 2008-10-31 | 2008-10-31 | メモリ装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010108569A JP2010108569A (ja) | 2010-05-13 |
| JP2010108569A5 JP2010108569A5 (enExample) | 2011-04-28 |
| JP5259343B2 true JP5259343B2 (ja) | 2013-08-07 |
Family
ID=42132983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008281316A Expired - Fee Related JP5259343B2 (ja) | 2008-10-31 | 2008-10-31 | メモリ装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7962838B2 (enExample) |
| JP (1) | JP5259343B2 (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4846384B2 (ja) * | 2006-02-20 | 2011-12-28 | 株式会社東芝 | 半導体記憶装置 |
| JP4836608B2 (ja) | 2006-02-27 | 2011-12-14 | 株式会社東芝 | 半導体記憶装置 |
| JP2007305267A (ja) * | 2006-05-15 | 2007-11-22 | Toshiba Corp | 半導体記憶装置 |
| JP4621715B2 (ja) * | 2007-08-13 | 2011-01-26 | 株式会社東芝 | メモリ装置 |
| JP2011165026A (ja) * | 2010-02-12 | 2011-08-25 | Toshiba Corp | エラー検出訂正システム |
| JP4982580B2 (ja) * | 2010-03-23 | 2012-07-25 | 株式会社東芝 | メモリシステム及びメモリシステムのデータ書き込み・読み出し方法 |
| JP5682253B2 (ja) * | 2010-11-22 | 2015-03-11 | 富士通株式会社 | プログラムおよび通信装置 |
| JP2012123600A (ja) | 2010-12-08 | 2012-06-28 | Toshiba Corp | メモリシステム及びメモリコントローラ |
| JP5204868B2 (ja) * | 2011-04-12 | 2013-06-05 | シャープ株式会社 | 半導体記憶装置 |
| KR101814476B1 (ko) | 2011-07-15 | 2018-01-05 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 구동 방법 |
| JP5458064B2 (ja) | 2011-07-14 | 2014-04-02 | 株式会社東芝 | 不揮発性半導体メモリ |
| US9904595B1 (en) | 2016-08-23 | 2018-02-27 | Texas Instruments Incorporated | Error correction hardware with fault detection |
| CN107124187B (zh) * | 2017-05-05 | 2020-08-11 | 南京大学 | 一种应用于闪存的基于等差校验矩阵的ldpc码译码器 |
| US10833707B2 (en) * | 2019-02-12 | 2020-11-10 | International Business Machines Corporation | Error trapping in memory structures |
| CN116192164A (zh) | 2022-12-30 | 2023-05-30 | 紫光同芯微电子有限公司 | 一种纠错码的译码方法、装置、设备及介质 |
Family Cites Families (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3418629A (en) * | 1964-04-10 | 1968-12-24 | Ibm | Decoders for cyclic error-correcting codes |
| US4099160A (en) * | 1976-07-15 | 1978-07-04 | International Business Machines Corporation | Error location apparatus and methods |
| US4058851A (en) * | 1976-10-18 | 1977-11-15 | Sperry Rand Corporation | Conditional bypass of error correction for dual memory access time selection |
| US4142174A (en) * | 1977-08-15 | 1979-02-27 | International Business Machines Corporation | High speed decoding of Reed-Solomon codes |
| EP0096165B1 (en) * | 1982-06-15 | 1988-06-08 | Kabushiki Kaisha Toshiba | Apparatus for dividing the elements of a galois field |
| JPS58219852A (ja) * | 1982-06-15 | 1983-12-21 | Toshiba Corp | エラ−訂正回路 |
| EP0096163B1 (en) * | 1982-06-15 | 1988-06-01 | Kabushiki Kaisha Toshiba | Apparatus for dividing the elements of a galois field |
| US4509172A (en) * | 1982-09-28 | 1985-04-02 | International Business Machines Corporation | Double error correction - triple error detection code |
| US4604655A (en) * | 1982-10-23 | 1986-08-05 | Pioneer Electronic Corporation | Method of recording and reproducing video format signal |
| US4567594A (en) * | 1983-06-07 | 1986-01-28 | Burroughs Corporation | Reed-Solomon error detecting and correcting system employing pipelined processors |
| US4677622A (en) * | 1983-06-22 | 1987-06-30 | Hitachi, Ltd. | Error correction method and system |
| EP0136587B1 (en) * | 1983-09-06 | 1991-04-17 | Kabushiki Kaisha Toshiba | Error correction circuit |
| US4841300A (en) * | 1986-06-18 | 1989-06-20 | Mitsubishi Denki K.K. | Error correction encoder/decoder |
| US4782490A (en) * | 1987-03-16 | 1988-11-01 | Cythera Corporation | Method and a system for multiple error detection and correction |
| US4958349A (en) * | 1988-11-01 | 1990-09-18 | Ford Aerospace Corporation | High data rate BCH decoder |
| JP2810397B2 (ja) * | 1989-02-16 | 1998-10-15 | キヤノン株式会社 | 誤り訂正装置 |
| US5040179A (en) * | 1989-08-18 | 1991-08-13 | Loral Aerospace Corp. | High data rate BCH encoder |
| JP2824474B2 (ja) * | 1992-02-17 | 1998-11-11 | 三菱電機株式会社 | 誤り訂正方式及びこの誤り訂正方式を用いた復号器 |
| EP0563491A1 (en) * | 1992-03-31 | 1993-10-06 | International Business Machines Corporation | Method and apparatus for implementing a triple error detection and double error correction code |
| US5710782A (en) * | 1995-12-28 | 1998-01-20 | Quantum Corporation | System for correction of three and four errors |
| US5761102A (en) * | 1995-12-28 | 1998-06-02 | Quantum Corporation | System and method for determining the cube root of an element of a galois field GF(2) |
| US5771246A (en) * | 1996-09-17 | 1998-06-23 | Quantum Corporation | Multiple-burst-correction system |
| KR100213254B1 (ko) * | 1996-10-18 | 1999-08-02 | 윤종용 | 에러 정정 방법 및 장치 |
| US5887005A (en) * | 1997-06-26 | 1999-03-23 | Integrated Device Technology, Inc. | Methods and apparatus for error correction |
| US5889793A (en) * | 1997-06-27 | 1999-03-30 | Integrated Device Technology, Inc. | Methods and apparatus for error correction |
| KR100260415B1 (ko) * | 1997-08-13 | 2000-07-01 | 윤종용 | 고속시리얼에러위치다항식계산회로 |
| US6199188B1 (en) * | 1997-10-07 | 2001-03-06 | Quantum Corporation | System for finding roots of degree three and degree four error locator polynomials over GF(2M) |
| US5978956A (en) * | 1997-12-03 | 1999-11-02 | Quantum Corporation | Five-error correction system |
| US6272659B1 (en) * | 1998-05-18 | 2001-08-07 | Cirrus Logic, Inc. | Error correction code processor employing adjustable correction power for miscorrection minimization |
| JP2000173289A (ja) | 1998-12-10 | 2000-06-23 | Toshiba Corp | エラー訂正可能なフラッシュメモリシステム |
| US6343367B1 (en) * | 1999-03-29 | 2002-01-29 | Maxtor Corporation | Error correction system for five or more errors |
| US6374383B1 (en) * | 1999-06-07 | 2002-04-16 | Maxtor Corporation | Determining error locations using error correction codes |
| US6360348B1 (en) * | 1999-08-27 | 2002-03-19 | Motorola, Inc. | Method and apparatus for coding and decoding data |
| US6560747B1 (en) * | 1999-11-10 | 2003-05-06 | Maxtor Corporation | Error counting mechanism |
| JP3975245B2 (ja) | 1999-12-16 | 2007-09-12 | 株式会社ルネサステクノロジ | 記録再生装置および半導体メモリ |
| US6651214B1 (en) * | 2000-01-06 | 2003-11-18 | Maxtor Corporation | Bi-directional decodable Reed-Solomon codes |
| US6643819B1 (en) * | 2000-01-26 | 2003-11-04 | Maxtor Corporation | Hybrid root-finding technique |
| JP3606569B2 (ja) * | 2001-03-09 | 2005-01-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 復号回路、該復号回路を用いる復号装置、復号方法および半導体デバイス |
| JP3447053B2 (ja) * | 2001-03-09 | 2003-09-16 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 組み合わせ回路、該組み合わせ回路を使用する符号化装置、復号装置、および半導体デバイス |
| JP4112849B2 (ja) * | 2001-11-21 | 2008-07-02 | 株式会社東芝 | 半導体記憶装置 |
| US7228467B2 (en) * | 2003-10-10 | 2007-06-05 | Quantum Corporation | Correcting data having more data blocks with errors than redundancy blocks |
| JP4791831B2 (ja) | 2006-01-20 | 2011-10-12 | 株式会社東芝 | 半導体記憶装置 |
| JP4836608B2 (ja) | 2006-02-27 | 2011-12-14 | 株式会社東芝 | 半導体記憶装置 |
| JP2007305267A (ja) * | 2006-05-15 | 2007-11-22 | Toshiba Corp | 半導体記憶装置 |
| JP4891704B2 (ja) * | 2006-08-28 | 2012-03-07 | 株式会社東芝 | 半導体記憶装置 |
| JP2010518464A (ja) | 2007-02-01 | 2010-05-27 | 株式会社東芝 | 半導体記憶装置 |
| JP4621715B2 (ja) * | 2007-08-13 | 2011-01-26 | 株式会社東芝 | メモリ装置 |
| US8433742B2 (en) * | 2008-08-06 | 2013-04-30 | Oracle America, Inc. | Modulus-based error-checking technique |
-
2008
- 2008-10-31 JP JP2008281316A patent/JP5259343B2/ja not_active Expired - Fee Related
-
2009
- 2009-09-08 US US12/555,507 patent/US7962838B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010108569A (ja) | 2010-05-13 |
| US20100115383A1 (en) | 2010-05-06 |
| US7962838B2 (en) | 2011-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5259343B2 (ja) | メモリ装置 | |
| JP4621715B2 (ja) | メモリ装置 | |
| JP2010518464A (ja) | 半導体記憶装置 | |
| US8468434B2 (en) | Error detection and correction system including a syndrome element calculating unit | |
| JPS59197940A (ja) | 誤り検出・補正メモリ | |
| JP2007305267A (ja) | 半導体記憶装置 | |
| US5668976A (en) | Error correction method and apparatus for disk drive emulator | |
| US9384083B2 (en) | Error location search circuit, and error check and correction circuit and memory device including the same | |
| JP4791831B2 (ja) | 半導体記憶装置 | |
| JPS6037833A (ja) | 符号語の複号装置及び読み取り装置 | |
| TWI479317B (zh) | Memory system | |
| JP4836608B2 (ja) | 半導体記憶装置 | |
| US8661319B2 (en) | Memory system | |
| JP4846384B2 (ja) | 半導体記憶装置 | |
| JP2012123600A (ja) | メモリシステム及びメモリコントローラ | |
| US10367529B2 (en) | List decode circuits | |
| JP4891704B2 (ja) | 半導体記憶装置 | |
| KR20230116051A (ko) | 프로그래밍가능 오류 정정 코드 인코딩 및 디코딩 로직 | |
| Chen et al. | An adaptive code rate EDAC scheme for random access memory | |
| KR102021560B1 (ko) | 오류 위치 탐색 회로, 그리고 그것을 포함하는 오류 검출 정정 회로 및 메모리 장치 | |
| CN117632577B (zh) | 一种基于bch编码的快速ecc纠错电路 | |
| JP2014057203A (ja) | ガロア体演算回路、及びメモリ装置 | |
| JP2014068058A (ja) | 誤り位置検索回路、誤り検出訂正回路、及びメモリ装置 | |
| JP2014064242A (ja) | 誤り検出訂正回路及び半導体メモリ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110315 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110315 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20121130 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121218 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130213 |
|
| RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20130221 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130402 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130424 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160502 Year of fee payment: 3 |
|
| LAPS | Cancellation because of no payment of annual fees |