JP5250502B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP5250502B2
JP5250502B2 JP2009181832A JP2009181832A JP5250502B2 JP 5250502 B2 JP5250502 B2 JP 5250502B2 JP 2009181832 A JP2009181832 A JP 2009181832A JP 2009181832 A JP2009181832 A JP 2009181832A JP 5250502 B2 JP5250502 B2 JP 5250502B2
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Japan
Prior art keywords
columnar member
conductive paste
pad
face
shield case
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JP2009181832A
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English (en)
Japanese (ja)
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JP2011035269A (ja
JP2011035269A5 (enrdf_load_stackoverflow
Inventor
孝 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009181832A priority Critical patent/JP5250502B2/ja
Publication of JP2011035269A publication Critical patent/JP2011035269A/ja
Publication of JP2011035269A5 publication Critical patent/JP2011035269A5/ja
Application granted granted Critical
Publication of JP5250502B2 publication Critical patent/JP5250502B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2009181832A 2009-08-04 2009-08-04 半導体装置及びその製造方法 Active JP5250502B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009181832A JP5250502B2 (ja) 2009-08-04 2009-08-04 半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009181832A JP5250502B2 (ja) 2009-08-04 2009-08-04 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2011035269A JP2011035269A (ja) 2011-02-17
JP2011035269A5 JP2011035269A5 (enrdf_load_stackoverflow) 2012-08-16
JP5250502B2 true JP5250502B2 (ja) 2013-07-31

Family

ID=43764027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009181832A Active JP5250502B2 (ja) 2009-08-04 2009-08-04 半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JP5250502B2 (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104185360B (zh) * 2014-08-18 2017-05-24 深圳市华星光电技术有限公司 一种印刷电路板及其设计方法
CN112309998B (zh) * 2019-07-30 2023-05-16 华为技术有限公司 封装器件及其制备方法、电子设备
JP2023103693A (ja) * 2022-01-14 2023-07-27 三菱電機株式会社 電子機器
WO2025121100A1 (ja) * 2023-12-04 2025-06-12 株式会社村田製作所 回路モジュール

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63107055A (ja) * 1986-06-02 1988-05-12 Fujitsu Ltd 集積回路用パッケ−ジ
JP2920066B2 (ja) * 1994-05-19 1999-07-19 株式会社東芝 半導体装置及びその製造方法
JP2809212B2 (ja) * 1996-07-30 1998-10-08 日本電気株式会社 電子装置パッケ−ジ
JP3798620B2 (ja) * 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
JP4494175B2 (ja) * 2004-11-30 2010-06-30 新光電気工業株式会社 半導体装置
JP2007042977A (ja) * 2005-08-05 2007-02-15 Shinko Electric Ind Co Ltd 半導体装置
JP5215587B2 (ja) * 2007-04-27 2013-06-19 ラピスセミコンダクタ株式会社 半導体装置

Also Published As

Publication number Publication date
JP2011035269A (ja) 2011-02-17

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