JP5229626B2 - ディープトレンチ構造を有する半導体素子の製造方法 - Google Patents
ディープトレンチ構造を有する半導体素子の製造方法 Download PDFInfo
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- JP5229626B2 JP5229626B2 JP2008332175A JP2008332175A JP5229626B2 JP 5229626 B2 JP5229626 B2 JP 5229626B2 JP 2008332175 A JP2008332175 A JP 2008332175A JP 2008332175 A JP2008332175 A JP 2008332175A JP 5229626 B2 JP5229626 B2 JP 5229626B2
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- 239000004065 semiconductor Substances 0.000 title claims description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000002955 isolation Methods 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 26
- 238000005468 ion implantation Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000010408 film Substances 0.000 description 57
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000010354 integration Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Description
12:パッド酸化膜、
14:パッド窒化膜、
16:第1の素子分離膜、
18:第2の素子分離膜、
20a、20b:ゲート酸化膜、
22a、22b:ゲート電極、
30a、30b:ソース/ドレイン領域、
40、40b:バルクイオン注入領域
Claims (6)
- (a)半導体基板にディープトレンチ構造を有する第1の素子分離膜を形成してNMOS領域とPMOS領域を分離するステップと、
(b)前記NMOS領域に前記第1の素子分離膜よりも浅い深さにドープされたPウェルを形成し、前記PMOS領域に前記第1の素子分離膜よりも浅い深さにドープされたNウェルを形成するステップと、
(c)前記PウェルにN型ドリフト領域を形成し、前記NウェルにP型ドリフト領域を形成するステップと、
(d)前記第1の素子分離膜より浅いトレンチ構造を有し、前記N型及びP型ドリフト領域の各々と第1の素子分離膜との間に複数の第2の素子分離膜を形成するステップと、
(e)前記NMOS領域と前記PMOS領域にそれぞれゲート酸化膜とゲート電極を形成するステップと、
(h)前記Nウェルの内部に形成された第2の素子分離膜と前記第1の素子分離膜との間に前記Nウェルと直に接触するN型バルクイオン注入領域を形成するステップと、
(i)前記Pウェルの上部に形成された第2の素子分離膜と前記第1の素子分離膜との間に前記Pウェルと直に接触するP型バルクイオン注入領域を形成するステップと
を含むことを特徴とするディープトレンチ構造を有する半導体素子の製造方法。 - (f)前記N型ドリフト領域にゲート電極を挟んでN型ソース領域とドレイン領域を形成するステップと、
(g)前記P型ドリフト領域にゲート電極を挟んでP型ソース領域とドレイン領域を形成するステップと、
をさらに含むことを特徴とする請求項1に記載のディープトレンチ構造を有する半導体素子の製造方法。 - 前記第1の素子分離膜は、3〜6μmの深さと0.4〜1.3μmの幅を有するように形成することを特徴とする請求項1に記載のディープトレンチ構造を有する半導体素子の製造方法。
- 前記複数の第2の素子分離膜は、0.7〜1.5μmの深さと0.3〜1.0μmの幅を有するように形成することを特徴とする請求項1に記載のディープトレンチ構造を有する半導体素子の製造方法。
- 前記複数の第2の素子分離膜は、
前記N型ドリフト領域及び前記P型ドリフト領域より更に深いことを特徴とする請求項1に記載のディープトレンチ構造を有する半導体素子の製造方法。 - 前記第1の素子分離膜は、
酸化膜とポリシリコン膜との二重層であることを特徴とする請求項1に記載のディープトレンチ構造を有する半導体素子の製造方法。
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KR1020070140352A KR101035596B1 (ko) | 2007-12-28 | 2007-12-28 | 딥 트렌치 구조를 갖는 반도체 소자 |
KR10-2007-0140352 | 2007-12-28 |
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US (1) | US8049283B2 (ja) |
JP (1) | JP5229626B2 (ja) |
KR (1) | KR101035596B1 (ja) |
TW (1) | TWI393247B (ja) |
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US9698044B2 (en) * | 2011-12-01 | 2017-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Localized carrier lifetime reduction |
JP6154582B2 (ja) | 2012-06-14 | 2017-06-28 | ラピスセミコンダクタ株式会社 | 半導体装置およびその製造方法 |
JP6154583B2 (ja) | 2012-06-14 | 2017-06-28 | ラピスセミコンダクタ株式会社 | 半導体装置およびその製造方法 |
US9076863B2 (en) | 2013-07-17 | 2015-07-07 | Texas Instruments Incorporated | Semiconductor structure with a doped region between two deep trench isolation structures |
CN104392961A (zh) * | 2014-12-11 | 2015-03-04 | 中国电子科技集团公司第四十七研究所 | 一种cmos集成电路的制造方法 |
US10121779B2 (en) * | 2016-12-13 | 2018-11-06 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with high current capacity and methods for producing the same |
US10892360B2 (en) | 2017-11-27 | 2021-01-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with high voltage device |
US11031303B1 (en) * | 2020-01-15 | 2021-06-08 | Taiwan Semiconductor Manufacturing Company Limited | Deep trench isolation structure and method of making the same |
CN111725299B (zh) * | 2020-07-14 | 2023-03-24 | 华虹半导体(无锡)有限公司 | Soi晶体管及其制造方法 |
CN114068534A (zh) * | 2021-11-15 | 2022-02-18 | 武汉新芯集成电路制造有限公司 | 半导体器件及其制造方法 |
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JPH01232739A (ja) * | 1988-03-12 | 1989-09-18 | Ricoh Co Ltd | 半導体装置の製造方法 |
JP3400528B2 (ja) * | 1994-04-01 | 2003-04-28 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
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JP3322239B2 (ja) * | 1999-04-30 | 2002-09-09 | 日本電気株式会社 | 半導体装置の製造方法 |
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JP4541980B2 (ja) * | 2005-06-27 | 2010-09-08 | シャープ株式会社 | 半導体装置 |
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US20090166744A1 (en) | 2009-07-02 |
KR20090072286A (ko) | 2009-07-02 |
US8049283B2 (en) | 2011-11-01 |
TW200937621A (en) | 2009-09-01 |
JP2009164609A (ja) | 2009-07-23 |
KR101035596B1 (ko) | 2011-05-19 |
TWI393247B (zh) | 2013-04-11 |
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