JP5221121B2 - 絶縁膜の形成方法 - Google Patents

絶縁膜の形成方法 Download PDF

Info

Publication number
JP5221121B2
JP5221121B2 JP2007336730A JP2007336730A JP5221121B2 JP 5221121 B2 JP5221121 B2 JP 5221121B2 JP 2007336730 A JP2007336730 A JP 2007336730A JP 2007336730 A JP2007336730 A JP 2007336730A JP 5221121 B2 JP5221121 B2 JP 5221121B2
Authority
JP
Japan
Prior art keywords
film
metal
sio
insulating film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007336730A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009158782A5 (https=
JP2009158782A (ja
Inventor
英夫 北川
尚武 北野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Anelva Corp
Canon Inc
Original Assignee
Canon Anelva Corp
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Anelva Corp, Canon Inc filed Critical Canon Anelva Corp
Priority to JP2007336730A priority Critical patent/JP5221121B2/ja
Priority to US12/342,349 priority patent/US7923360B2/en
Priority to CN2008101906925A priority patent/CN101471255B/zh
Priority to KR1020080135473A priority patent/KR101138273B1/ko
Publication of JP2009158782A publication Critical patent/JP2009158782A/ja
Publication of JP2009158782A5 publication Critical patent/JP2009158782A5/ja
Application granted granted Critical
Publication of JP5221121B2 publication Critical patent/JP5221121B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6928—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H10P14/693—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/0135—Making the insulator by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
    • H10P14/6524—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6319—Formation by plasma treatments, e.g. plasma oxidation of the substrate

Landscapes

  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2007336730A 2007-12-27 2007-12-27 絶縁膜の形成方法 Expired - Fee Related JP5221121B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007336730A JP5221121B2 (ja) 2007-12-27 2007-12-27 絶縁膜の形成方法
US12/342,349 US7923360B2 (en) 2007-12-27 2008-12-23 Method of forming dielectric films
CN2008101906925A CN101471255B (zh) 2007-12-27 2008-12-26 形成介电膜的方法
KR1020080135473A KR101138273B1 (ko) 2007-12-27 2008-12-29 절연막의 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007336730A JP5221121B2 (ja) 2007-12-27 2007-12-27 絶縁膜の形成方法

Publications (3)

Publication Number Publication Date
JP2009158782A JP2009158782A (ja) 2009-07-16
JP2009158782A5 JP2009158782A5 (https=) 2011-01-27
JP5221121B2 true JP5221121B2 (ja) 2013-06-26

Family

ID=40799022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007336730A Expired - Fee Related JP5221121B2 (ja) 2007-12-27 2007-12-27 絶縁膜の形成方法

Country Status (4)

Country Link
US (1) US7923360B2 (https=)
JP (1) JP5221121B2 (https=)
KR (1) KR101138273B1 (https=)
CN (1) CN101471255B (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7723205B2 (en) * 2005-09-27 2010-05-25 Semiconductor Energy Laboratory Co., Ltd Semiconductor device, manufacturing method thereof, liquid crystal display device, RFID tag, light emitting device, and electronic device
WO2009031232A1 (ja) * 2007-09-07 2009-03-12 Canon Anelva Corporation スパッタリング方法および装置
US8148275B2 (en) * 2007-12-27 2012-04-03 Canon Kabushiki Kaisha Method for forming dielectric films
WO2010050291A1 (ja) 2008-10-31 2010-05-06 キヤノンアネルバ株式会社 誘電体膜、誘電体膜の製造方法、半導体装置、および、記録媒体
JP4494525B1 (ja) * 2008-10-31 2010-06-30 キヤノンアネルバ株式会社 誘電体膜の製造方法、半導体装置の製造方法、誘電体膜、およびコンピュータ読み取り可能な記録媒体
JP5247619B2 (ja) * 2009-07-28 2013-07-24 キヤノンアネルバ株式会社 誘電体膜、誘電体膜を用いた半導体装置の製造方法及び半導体製造装置
JP2011151366A (ja) * 2009-12-26 2011-08-04 Canon Anelva Corp 誘電体膜の製造方法
JP5937297B2 (ja) * 2010-03-01 2016-06-22 キヤノンアネルバ株式会社 金属窒化膜、該金属窒化膜を用いた半導体装置、および半導体装置の製造方法
DE112011104624B4 (de) 2010-12-28 2019-01-24 Canon Anelva Corporation Verfahren zum Herstellen einer Halbleitervorrichtung
US8993058B2 (en) * 2012-08-28 2015-03-31 Applied Materials, Inc. Methods and apparatus for forming tantalum silicate layers on germanium or III-V semiconductor devices
WO2018134024A1 (en) * 2017-01-17 2018-07-26 Zf Friedrichshafen Ag Method of manufacturing an insulation layer on silicon carbide

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE417275T1 (de) * 1997-09-22 2008-12-15 Novartis Vaccines & Diagnostic Puffern zur stabilizierung von hcv antigenen
WO2001082346A1 (en) 2000-04-24 2001-11-01 Beijing Normal University Method for fabricating silicon-on-insulator
JP3944367B2 (ja) 2001-02-06 2007-07-11 松下電器産業株式会社 絶縁膜の形成方法及び半導体装置の製造方法
US6720241B2 (en) 2001-06-18 2004-04-13 Matsushita Electric Industrial Co., Ltd. Method for manufacturing semiconductor device
JP3746968B2 (ja) 2001-08-29 2006-02-22 東京エレクトロン株式会社 絶縁膜の形成方法および形成システム
AU2003281112A1 (en) 2002-07-16 2004-02-02 Nec Corporation Semiconductor device, production method and production device thereof
US7144825B2 (en) * 2003-10-16 2006-12-05 Freescale Semiconductor, Inc. Multi-layer dielectric containing diffusion barrier material
JP2005222977A (ja) * 2004-02-03 2005-08-18 Hitachi Ltd 半導体装置の製造方法
JP2005311061A (ja) * 2004-04-21 2005-11-04 Nippon Telegr & Teleph Corp <Ntt> 絶縁層及びその製造方法
KR101117450B1 (ko) * 2006-03-09 2012-03-13 어플라이드 머티어리얼스, 인코포레이티드 낮은 에너지 플라즈마 시스템을 이용하여 하이 유전상수 트랜지스터 게이트를 제조하는 방법 및 장치
US7645710B2 (en) 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system

Also Published As

Publication number Publication date
KR20090071505A (ko) 2009-07-01
US20090170340A1 (en) 2009-07-02
KR101138273B1 (ko) 2012-04-24
CN101471255A (zh) 2009-07-01
JP2009158782A (ja) 2009-07-16
CN101471255B (zh) 2012-08-29
US7923360B2 (en) 2011-04-12

Similar Documents

Publication Publication Date Title
JP5221121B2 (ja) 絶縁膜の形成方法
JP3937892B2 (ja) 薄膜形成方法および半導体装置の製造方法
US6303481B2 (en) Method for forming a gate insulating film for semiconductor devices
US7964514B2 (en) Multiple nitrogen plasma treatments for thin SiON dielectrics
TWI553734B (zh) 用於半導體元件之低溫氧化的方法
CN101471254B (zh) 形成介电膜的方法
JP2009545895A (ja) 希ガスを含有するダブルプラズマ窒化物形成によるＣＭＯＳＳｉＯＮゲート誘電性能の改善
CN101944482B (zh) 形成介电膜的方法
CN100468638C (zh) 半导体元件的制造方法
JP2016063232A (ja) ＳｉＮの堆積
CN1659692A (zh) 基板处理方法
KR101078498B1 (ko) 절연체 박막의 제조 방법
JP3746478B2 (ja) 半導体装置の製造方法
CN101620995A (zh) 栅极介质层及其制造方法、半导体器件及其制造方法
JP4584356B2 (ja) 基板処理方法、基板処理装置、ｍｏｓ−ｆｅｔの製造方法、不揮発メモリの製造方法、およびコンピュータ読み取り可能な記録媒体
JP2008532282A (ja) 窒化ゲート誘電体を形成する方法
CN101471256A (zh) 形成介电膜的方法
JP2009158784A (ja) 絶縁膜の形成方法
CN101120437B (zh) 电介质膜及其形成方法
JP2005079563A (ja) 電子デバイスの製造方法
JP5141321B2 (ja) 半導体装置の製造方法
JP4629325B2 (ja) トランジスタの製造方法
JP2006216774A (ja) 絶縁膜の成膜方法
WO2007124197A2 (en) Method for forming silicon oxynitride materials

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20100617

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100730

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101207

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101207

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20101227

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110705

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20120919

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20120919

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20121016

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20121102

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121122

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130118

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130121

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130207

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130307

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160315

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5221121

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees