JP5219764B2 - 有機の光放射材料を使用するディスプレイタイル構造 - Google Patents
有機の光放射材料を使用するディスプレイタイル構造 Download PDFInfo
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- JP5219764B2 JP5219764B2 JP2008312310A JP2008312310A JP5219764B2 JP 5219764 B2 JP5219764 B2 JP 5219764B2 JP 2008312310 A JP2008312310 A JP 2008312310A JP 2008312310 A JP2008312310 A JP 2008312310A JP 5219764 B2 JP5219764 B2 JP 5219764B2
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- Physics & Mathematics (AREA)
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- Multimedia (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
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Description
複数ビューワを必要とする用途
ユーザーがエリアでを中心として移動する必要がある用途
実世界のシミュレーションがトレーニングのために必要とされる用途。
図で示す例示的な実施形態に関して、本発明を説明する。図面は、寸法を正しく表してはいない。実際に、図面の寸法は、本発明の説明の補助のため誇張されている。本発明は光学の発光ダイオード(OLED)ディスプレイデバイスに関して説明されるが、電界発光、発光ダイオード(LED)、プラスマ技術等の他の放射ディスプレイテクノロジー、又は双安定反射コレステリック(BRC)液晶技術等の反射ディスプレイテクノロジーで行われることができることも考慮されている。
1つは、金属層又は絶縁構造の基板であるだろう。層516は、カラムバイア520とローバイア522を有するセラミック層である。セラミック層516の上で形成されるローバイアは、例示的なディスプレイタイルのロー電極524に接続する。
タングステン、金又は銅などの金属から、ポリシリコンから、又は、そのような導体を含む多層構造から形成されるだろう。
。
だろう。非常になめらかな表面(例えばスピンオンガラス)を形成する多数の材料で、平坦化層は、形成されるだろう。次に、ディスプレイ材料526が、ロー電極524上で堆積される。ディスプレイ材料526を堆積させた後に、カラム電極は、ITOを堆積させるために従来のプロセスを使用しているタイルの上で形成される。
、障壁層であるという更なる利点を提供するだろう。
電極は、そして、想像線で示すバイア816によってエレクトロニクスセクションに結合する。三重のサブピクセル構造の幾何学は、dSH(サブピクセルの高さ)、dSW(サブピクセルの幅)とde(アクティブサブピクセルエリアから画素エリアのエッジへの距離)によって定義される。本発明の1つの例示的な実施形態に対して、これらの寸法は、画素ピッチ(P)に関して表1で与えられる。
dSH .5P
dSW .16P
de .25P
その基板層の範囲内の電極のための数接点層がバイアの数によって拘束されない点に留意する必要がある。マルチプル接点は、単一バイアから枝分かれするだろう。
dSH .25P
dSW .25P
de .125P
dSI .25P
図6A及び6Bが、水平及び垂直方向で等しい距離deとdSIを示す一方、これらの値が異なるだろうことが企図される。図6Aと6Bで示す例示的な画素構造は、両方とも、ほぼ画素エリアの25のパーセントをカバーしているアクティブ画素部分を有し、ほぼ25のパーセントの画素アパーチャーを生じる。この値は、例示的なだけである。本発明は、両方のより大きく及びより小さな画素アパーチャーを企図する。
0は、タイル120の間のギャップ2012の両側にそれらの画素を含むディスプレイの全ての画素の間に位置するように整列するだろう。ブラックラインの光学のインテグレータパターンは、また、いくつかの光学のインテグレータ構造のブラックラインのディスプレイタイルの間のギャップの上部の上で位置し、それらの鮮明度をブロックする点で縦仕切りに似ている。組み立てられるとき、タイル120のガラス製の基板532は、透明シート2020の後ろの表面の上で、ブラックライン2010に隣接して配置され、集積構造を形成する。
ラックラインの均等なパターンを見る。
に異なって散乱する場合、例えば、エッジは表示されたイメージでの低減された輝度のバンドとして見えるだろう。縦仕切りの上部バーの下側1614と横の表面1612のうちの1つ以上は、それが接合する2枚のタイルに、縦仕切り1512を付けるために接着材で覆われているだろう。これらの表面の全てが接着材で覆われているならば、縦仕切りは、ディスプレイデバイスにタイルを接合するために使用されるだろう。
本発明の例示的な実施形態で、nglass = 1.55、θc≒40°である。
線をブロックする。このように、このブラックストライプはギャップ領域をオブザーバーに見えなくする。実際問題として、ブラックストライプは、ギャップのあらゆる有限幅に対して2dcよりわずかに広い必要があるだろう。
2020の後ろの表面の間であらゆるギャップを最小にするために可能な限り、縦仕切りの上部バーを狭くすることは望ましいだろう。或いは、縦仕切り1512はブラックマトリクスラインで積分構造2020上へ組み立てられるだろう。この構成で、縦仕切りはタイル120が合成ディスプレイを形成するために挿入されるポケットを形成する。この構造は、接着材を使用積分構造2020に直接に縦仕切りを接着し、次に、ディスプレイにタイルを挿入する前に接着材をクロスバー1610の下側とステムの側に加えるすることによって形成されるだろう。
Claims (8)
- 上面および底面を備える基板と、
前記基板の前記上面に接続され、ローおよびカラムを有するマトリクス状に配列され、前記マトリクスの前記ローおよびカラムに対応する複数のコンタクトを備える複数のピクセル構造であって、各ピクセル構造が表示材料を含む区別可能な部分を含み、前記表示材料と他のピクセル構造の表示材料とが物理的に離れている、複数のピクセル構造と、
前記基板の前記底面に接続されたピクセル駆動回路であって、前記ローおよびカラムを有するマトリクス状に配列されたピクセル構造を選択的に活性化する複数の電気信号を出力するようになっているピクセル駆動回路と、
前記基板の前記底面に接続されたタイミング回路であって、前記ピクセル駆動回路を連続的にスキャンし、同期したタイミング信号を受けて前記ピクセル構造の前記マトリクスの連続したローへ電気信号を選択的に出力するように構成されたタイミング回路と、
前記ピクセル駆動回路からの複数の電気信号を受信するように接続され、前記マトリクス状に配列された前記ピクセル構造の前記複数のコンタクトのうちの少なくとも1つにそれぞれが対応している複数の電気コンタクトと、
前記複数の電気コンタクトと前記マトリクス状に配列された前記ピクセル構造の電極とが接続されるときに経由される複数のバイアと、
前記ピクセル駆動回路およびタイミング回路の少なくとも1つのコンポーネントを前記基板へ接続するための接続材料と
を備え、
前記少なくとも1つのコンポーネントを接続するための前記接続材料は、前記少なくと1つのコンポーネントと前記基板とが接触しないように、前記基板の前記底面へ接続され、前記接続材料はフィン構造を含み、前記フィン構造が前記少なくとも1つのコンポーネントと前記基板とを接続し且つ前記基板上に直接取り付けられて放熱器として作用する、電子表示構造物。 - 電子表示構造物であって、
上面および底面を備える基板と、
前記基板の前記上面に接続され、ローおよびカラムを有するマトリクス状に配列され、前記マトリクスのローおよびカラムに対応する複数のコンタクトを備える複数のピクセル構造であって、各ピクセル構造が表示材料を含む区別可能な部分を含み、前記表示材料と前記電子表示構造物の他のピクセル構造の表示材料とは物理的に離れている、複数のピクセル構造と、
前記基板の前記底面に接続されたピクセル駆動回路であって、前記ローおよびカラムを有するマトリクス状に配列されたピクセル構造を選択的に活性化する複数の電気信号を出力するようになっているピクセル駆動回路と、
前記基板の前記底面に接続されたタイミング回路であって、前記ピクセル駆動回路を連続的にスキャンし、同期したタイミング信号を受けて前記ピクセル構造の前記マトリクスの連続したローへ電気信号を選択的に出力するように構成されたタイミング回路と、
前記ピクセル駆動回路からの複数の電気信号を受信するように接続され、前記マトリクス状に配列された前記ピクセル構造の前記複数のコンタクトのうちの少なくとも1つにそれぞれが対応している複数の電気コンタクトと、
前記複数の電気コンタクトと前記マトリクス状に配列された前記ピクセル構造の電極とが接続されるときに経由される複数のバイアと、
前記ピクセル駆動回路およびタイミング回路と前記基板とを、前記基板にホットスポットが形成されないように接続するための接続材料と
を備え、
前記少なくと1つのコンポーネントを接続するための接続材料が前記基板の前記底面に接続され、前記接続材料はフレキシブル回路基板を含み、前記フレキシブル回路基板の一部分は前記基板の前記底面から離れる角度で延び、前記接続材料は、前記少なくと1つのコンポーネントと前記フレキシブル回路基板の前記一部分とを、前記少なくとも1つのコンポーネントが前記基板に直接接触しないように接続している、電子表示構造物。 - 前記複数のピクセル構造は複数のディスプレイタイルで構成された格子配列を形成し、各ディスプレイタイルは複数ピクセル構造のサブセットを含み、前記複数のディスプレイタイルは前記ディスプレイタイル間の目に見える継ぎ目を最小限にするように構成される、請求項1又は2に記載の電子表示構造物。
- 各ディスプレイタイルが、個々のピクセル構造の明るさを絶えず調節する補償システムを実現する回路をさらに備える、請求項3に記載の電子表示構造物。
- 前記補償システムは、特定のピクセル構造に関する電流および時間を測定し、電流と時間の積を積分することによってピクセルの明るさを求める、請求項4に記載の電子表示構造物。
- 前記補償システムは、各ピクセル構造に印加される電圧を監視し、ピクセルの明るさの変化に対する電圧変化に関する比例定数を求めることによって明るさの減衰を補正する、請求項4に記載の電子表示構造物。
- 前記補償システムは、センサを用いて各ピクセル構造に関する明るさデータを収集することによってピクセルの明るさの減衰を補正する、請求項4に記載の電子表示構造物。
- 前記収集された明るさのデータは、減衰したピクセルの明るさを補正するのに必要な電圧を求めるための表示駆動回路に送られる、請求項7に記載の電子表示構造物。
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EP2330627A2 (en) | 2011-06-08 |
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EP1332487A2 (en) | 2003-08-06 |
WO2002047310A3 (en) | 2002-09-12 |
EP2330627A3 (en) | 2011-11-02 |
JP2009110014A (ja) | 2009-05-21 |
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